US 2024/0426909 A1Published application

Logic bist circuit and semiconductor device including same

AssigneeSamsung Electronics Co., Ltd.

InventorsSangsoon IM, Sungcheol PARK

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Abstract

Provided are a logic built-in self-test (BIST) circuit that performs a scan test improving test coverage for each clock domain and a semiconductor device including the logic BIST circuit. The logic BIST circuit includes an OR gate configured to receive a scan enable signal and a register setting signal, and generate a modified scan enable signal; a clock gating circuit configured to output an enable clock irrespective of a function enable signal when the register setting signal has a first logic value, and a scan chain configured to capture an output of a first logic circuit connected to flip-flops according to the enable clock.

Claims19

Dependent claims

A logic built-in self-test (BIST) circuit comprising:

a first OR gate configured to receive a scan enable signal and a first register setting signal, and generate a first modified scan enable signal;
a first clock gating circuit configured to receive a first clock and output a first enable clock, according to the first modified scan enable signal and a first function enable signal;
a first scan chain configured to load first scan data into first flip-flops according to the first enable clock, capture an output of a first logic circuit connected to the first flip-flops, and output captured data;
a second OR gate configured to receive the scan enable signal and a second register setting signal, and generate a second modified scan enable signal;
a second clock gating circuit configured to receive a second clock and output a second enable clock, according the second modified scan enable signal and a second function enable signal;
and
a second scan chain configured to load second scan data into second flip-flops according to the second enable clock, capture an output of a second logic circuit connected to the second flip-flops, and output the captured data,
wherein at least one of the first clock gating circuit and the second clock gating circuit is configured to output a corresponding enable clock, irrespective of a corresponding function enable signal, when a corresponding register setting signal has a first logic value.

5 more elements

A logic built-in self-test (BIST) circuit comprising:

a decompressor configured to sequentially generate a plurality of test patterns;
a pattern counter configured to count a number of the plurality of test patterns and generate counting signals;
a first OR gate configured to receive a scan enable signal and a first counting signal among the counting signals and generate a first modified scan enable signal;
a first clock gating circuit configured to receive a first clock and output a first enable clock, according to the first modified scan enable signal and a first function enable signal;
and
a first scan chain configured to load first scan data into first flip-flops according to the first enable clock, capture an output of a first logic circuit connected to the first flip-flops, and output captured data,
wherein the first clock gating circuit is further configured to, when the first counting signal has a first logic value, output the first enable clock irrespective of a state of the first function enable signal.

4 more elements

A logic built-in self-test (BIST) circuit comprising:

a decompressor configured to sequentially generate a plurality of test patterns;
a pattern counter configured to count a number of the plurality of test patterns generated by the decompressor and generate counting signals;
a pulse generator configured to receive at least some of the counting signals and generate pulse signals;
a first OR gate configured to receive a scan enable signal and a first pulse signal among the pulse signals and generate a first modified scan enable signal;
a first clock gating circuit configured to receive a first clock and output a first enable clock, according to the first modified scan enable signal and a first function enable signal;
and
a first scan chain configured to load first scan data into first flip-flops according to the first enable clock, and capture and output an output of a first logic circuit connected to the first flip-flops.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/659,942Filed 9 May 2024
Priority: KR 10-2023-008067922 Jun 2023
Published: 26 Dec 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G01R 31/318552
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: clock circuits details
G01R 31/318555
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: control logic
G01R 31/31727
Testing of digital circuits: clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing…
G01R 31/3177
Testing of digital circuits: testing of logic operation, e.g. by logic analysers

Family

US 12,455,317 B2Related patent
US 2024/0426909 A1This patent

From the US filing history. Foreign family members aren’t listed.

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