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US 12,066,488 B2Granted
Embedded PHY (EPHY) IP core for FPGA
AssigneeSanDisk Technologies LLC
InventorsDoron Ganon, Eitan Lerner
Life of this patent
Estimating the term…
Abstract
The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYS (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.
Claims19
A testing device, comprising:
- a field programmable gate array (FPGA);
- and
- an embedded physical layer (EPHY), the EPHY including:
- a logic portion having a first logical phy and a second logical phy, wherein the logic portion is disposed in the FPGA, and wherein the logic portion communicates with the FPGA through the first and second logical phys;
- and
- a glue hardware portion, wherein the logic portion communicates with a device under test (DUT) through the glue hardware portion, the glue hardware portion including:
- a first differential amplifier;
- and
- a first multiplexer (MUX) coupled to the first differential amplifier and the FPGA via a first line, wherein the testing device is capable of receiving and sending signals to and from the DUT at a first speed, wherein the testing device is capable of receiving and sending signals to and from the DUT at a second speed, wherein the second speed is greater than the first speed, and wherein the first differential amplifier is configured to reduce or increase the signals sent and received at the first speed or the signals sent and received at the second speed.
6 more elements
A testing device, comprising:
- a field programmable gate array (FPGA) comprising a controller;
- and
- an embedded physical layer (EPHY) coupled to the controller, the EPHY including:
- a logic portion comprising a low speed interface and a high speed interface, wherein the logic portion is disposed in the FPGA, and wherein the logic portion communicates with the FPGA through the low speed interface and the high speed interface;
- and
- a glue hardware portion, wherein the logic portion communicates with a device under test (DUT) through the glue hardware portion, the glue hardware portion comprising:
- a plurality of transmission multiplexers (MUXs);
- a plurality of receiving MUXs;
- and
- a plurality of differential amplifiers, wherein the testing device is capable of receiving and sending signals to and from the DUT at a first speed, wherein the testing device is capable of receiving and sending signals to and from the DUT at a second speed, wherein the second speed is greater than the first speed, and wherein:
- the low speed interface is coupled to a first transmission MUX of the plurality of transmission MUXs;
- the low speed interface is coupled to a first receiving MUX of the plurality of receiving MUXs;
- the high speed interface is coupled to a second transmission MUX of the plurality of transmission MUXs;
- and
- the high speed interface is coupled to a second receiving MUX of the plurality of receiving MUXs.
12 more elements
A testing device, comprising:
- a field programmable gate array (FPGA) comprising a controller;
- and
- an embedded physical layer (EPHY) coupled to the controller, the EPHY including:
- a logic portion comprising a low speed interface and a high speed interface, wherein the logic portion is disposed in the FPGA, and wherein the logic portion communicates with the FPGA through the low speed interface and the high speed interface;
- and
- a glue hardware portion, wherein the logic portion communicates with a device under test (DUT) through the glue hardware portion, the glue hardware portion comprising:
- a plurality of transmission multiplexers (MUXs);
- a plurality of receiving MUXs;
- and
- a plurality of differential amplifiers, wherein the testing device is capable of receiving and sending signals to and from the DUT at a first speed, wherein the testing device is capable of receiving and sending signals to and from the DUT at a second speed, wherein the second speed is greater than the first speed, and wherein:
- the low speed interface is coupled to a first transmission MUX of the plurality of transmission MUXs and a first differential amplifier of the plurality of differential amplifiers;
- the low speed interface is coupled to a first receiving MUX of the plurality of receiving MUXs and a second differential amplifier of the plurality of differential amplifiers;
- the high speed interface is coupled to a second transmission MUX of the plurality of transmission MUXs and a third differential amplifier of the plurality of differential amplifiers;
- and
- the high speed interface is coupled to a second receiving MUX of the plurality of receiving MUXs and a fourth differential amplifier of the plurality of differential amplifiers.
12 more elements
Dependencies are inferred from the claim text.