G01R 31/318321
For combinational circuits
Official title: {for combinational circuits}
G01R31/318321 (For combinational circuits) appears on 28 US grants and 15 published applications in this corpus.
Search patents in G01R- Granted patents
- 28
- Published applications
- 15
- Assignees
- 23
- Inventors
- 57
- Latest grant
- 12 Nov 2024
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1987 | 2 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 2 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 1 | 0 |
| 1995 | 0 | 0 |
| 1996 | 1 | 0 |
| 1997 | 1 | 0 |
| 1998 | 2 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 1 | 0 |
| 2002 | 1 | 2 |
| 2003 | 2 | 1 |
| 2004 | 0 | 2 |
| 2005 | 1 | 0 |
| 2006 | 3 | 1 |
| 2007 | 1 | 0 |
| 2008 | 0 | 0 |
| 2009 | 0 | 2 |
| 2010 | 1 | 0 |
| 2011 | 1 | 0 |
| 2012 | 0 | 0 |
| 2013 | 0 | 0 |
| 2014 | 0 | 0 |
| 2015 | 0 | 0 |
| 2016 | 0 | 0 |
| 2017 | 0 | 1 |
| 2018 | 1 | 0 |
| 2019 | 1 | 1 |
| 2020 | 0 | 1 |
| 2021 | 0 | 1 |
| 2022 | 2 | 1 |
| 2023 | 0 | 0 |
| 2024 | 3 | 2 |
By publication year. Applications have been published since 2001.
Recent patents
- Integrating machine learning delay estimation in FPGA-based emulation systems12 Nov 2024US 12,140,628 B2Synopsys, Inc.
- Scan tree construction17 Sep 2024US 12,092,691 B2Tsinghua University
- Machine learning delay estimation for emulation systems2 Jan 2024US 11,860,227 B2Synopsys, Inc.
- Semiconductor integrated circuit having scan chains sequentially supplied with a clock signal6 Dec 2022US 11,519,963 B2Kioxia Corporation
- Testing device and testing method for testing a device under test22 Mar 2022US 11,280,833 B2Rohde & Schwarz GmbH & Co.KG
- Scan Tree Construction9 May 2024US 2024/0151771 A1Tsinghua University
- Integrating Machine Learning Delay Estimation in FPGA-Based Emulation Systems21 Mar 2024US 2024/0094290 A1Synopsys, Inc.
- Machine learning delay estimation for emulation systems16 Jun 2022US 2022/0187367 A1Synopsys, Inc.
- Semiconductor integrated circuit5 Aug 2021US 2021/0239759 A1Kioxia Corporation
- Testing device and testing method for testing a device under test9 Jul 2020US 2020/0217891 A1Rohde & Schwarz GmbH & Co.KG
Most cited
By later US patents
- Cell architecture to reduce customization in a semiconductor device278US 6,580,289 B2ViASIC, Inc. · 2003
- Built in self test input generator for programmable logic arrays33US 4,672,610 AMotorola, Inc. · 1987
- Output pin for selectively outputting one of a plurality of signals internal to a semiconductor chip according to a programmable register for diagnostics22US 5,717,695 ASilicon Graphics, Inc. · 1998
- Method for monitoring and improving integrated circuit fabrication using FPGAs14US 7,020,860 B1Xilinx, Inc. · 2006
- Device and method for the generation of test vectors and testing method for integrated circuits13US 5,010,552 AThomson-CSF · 1991