Semiconductor integrated circuit having scan chains sequentially supplied with a clock signal
AssigneeKioxia Corporation
InventorMasaki Ooiso
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit includes scan chains, each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an integrated clock gating (ICG) chain composed by coupling, to one another, ICG circuits, each of which individually supplies a corresponding one of the scan chains with a circuit clock signal to operate the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at respective timings that are different among the scan chains.
Claims19
A semiconductor integrated circuit, comprising:
- a plurality of scan chains, each of which includes a serial connection of a plurality of sequential circuits, and performs a shift register operation;
- and
- an integrated clock gating (ICG) chain including a plurality of ICG circuits, each of which individually supplies a corresponding one of the scan chains with a circuit clock signal to operate the sequential circuits,
- wherein the ICG chain is coupled by a signal line,
- wherein an ICG enable propagation signal that propagates through the signal line is sequentially input to the ICG circuits, and
- wherein, in response to the input of the ICG enable propagation signal, each of the ICG circuits supplies the corresponding one of the scan chains with the circuit clock signal.
A method for controlling a semiconductor integrated circuit including a plurality of scan chains, each of which includes a serial connection of a plurality of sequential circuits, the method comprising:
- supplying the scan chains with circuit clock signals to operate the sequential circuits at respective timings that are different among the scan chains;
- and
- causing the scan chains to perform shift register operations in an order in which the scan chains are supplied with the circuit clock signals,
- wherein an integrated clock gating (ICG) chain is configured by coupling, via a signal line, a plurality of ICG circuits, each of which individually supplies a corresponding one of the scan chains with the circuit clock signal,
- an ICG enable propagation signal is propagated through the signal line and is sequentially input to the ICG circuits, and
- in each of the ICG circuits, in response to the input of the ICG enable propagation signal, the corresponding one of the scan chains is supplied with the circuit clock signal.
Dependencies are inferred from the claim text.