US 12,140,628 B2 · Integrating machine learning delay estimation in FPGA-based emulation systems

Abstract

A method or system for estimating delays in design under tests (DUTs) using machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays, along with the corresponding feature vectors, are used to train a machine learning delay model. The trained model is designed to receive a combinatorial path of a DUT as input and generate an estimated wire delay as output. This approach leverages machine learning to predict delays in electronic designs, improving the efficiency and accuracy of delay estimations in complex circuits.

Claims20

Dependent claims

A non-transitory computer readable medium comprising stored instructions, wherein the stored instructions, when executed by one or more processors, cause the one or more processors to:

access a plurality of design under tests (DUTs), each of the plurality of DUTs comprising a plurality of logic blocks;
for each of the plurality of DUTs,
identify a combinatorial path based on the plurality of logic blocks of the DUT, the combinatorial path connecting one or more logic blocks of the plurality of logic blocks;
generate a feature vector including values of one or more orthogonal features representing characteristics of the combinatorial path;
compile the DUT for emulation;
and
measure delay of the combinatorial path of the compiled DUT;
and
train a machine learning delay model using the measured delays of the combinatorial paths of the plurality of compiled DUTs and corresponding feature vectors, the machine learning delay model trained to:
receive a combinatorial path of a DUT as input;
and
generate an estimated wire delay as output.

9 more elements

A method for delay estimation, the method comprising:

accessing a plurality of design under tests (DUTs), each of the plurality of DUTs comprising a plurality of logic blocks;
for each of the plurality of DUTs,
identifying a combinatorial path based on the plurality of logic blocks of the DUT, the combinatorial path connecting one or more logic blocks of the plurality of logic blocks;
generating a feature vector including values of one or more orthogonal features representing characteristics of the combinatorial path;
compiling the DUT for emulation;
and
measuring delay of the combinatorial path of the compiled DUT;
and
training a machine learning delay model using the measured delays of the combinatorial paths of the plurality of compiled DUTs and corresponding feature vectors,
wherein the machine learning delay model is trained to:
receive a combinatorial path of a DUT as input;
and
generate an estimated wire delay as output.

10 more elements

A computing system, the system comprising:

one or more processors;
and
a non-transitory computer readable memory, comprising stored instructions, wherein the stored instructions, when executed by the one or more processors, cause the one or more processors to:
access a plurality of design under tests (DUTs), each of the plurality of DUTs comprising a plurality of logic blocks;
for each of the plurality of DUTs,
identify a combinatorial path based on the plurality of logic blocks of the DUT, the combinatorial path connecting one or more logic blocks of the plurality of logic blocks;
generate a feature vector including values of one or more orthogonal features representing characteristics of the combinatorial path;
compile the DUT for emulation;
and
measure delay of the combinatorial path of the compiled DUT;
and
train a machine learning delay model using the measured delays of the combinatorial paths of the plurality of compiled DUTs and corresponding feature vectors,
wherein the machine learning delay model is trained to:
receive a combinatorial path of a DUT as input;
and
generate an estimated wire delay as output.

13 more elements

Dependencies are inferred from the claim text.

Integrating machine learning delay estimation in FPGA-based emulation systems

Life of this patent

Integrating machine learning delay estimation in FPGA-based emulation systems

Life of this patent

Abstract

Claims20