Semiconductor integrated circuit
AssigneeKioxia Corporation
InventorMasaki OOISO
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit includes: scan chains each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an ICG chain composed by coupling, to one another, ICG circuits each of which individually supplies any of the scan chains with a circuit clock signal for operating the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at pieces of timing which are different between the scan chains.
Claims20
A semiconductor integrated circuit comprising:
- a plurality of scan chains each of which includes a serial connection of a plurality of sequential circuits, and performs a shift register operation;
- and
- an ICG chain including a plurality of ICG circuits each of which individually supplies any of the scan chains with a circuit clock signal for operating the sequential circuits,
- wherein the ICG chain is coupled by a signal line,
- wherein an ICG enable propagation signal that propagates through the signal line is sequentially input to the ICG circuits, and
- wherein, in response to the input of the ICG enable propagation signal, each of the ICG circuits supplies the scan chain with the circuit clock signal.
The semiconductor integrated circuit according to claim
- wherein each of the scan chains has a configuration in which a plurality of partial scan chains are connected in series to one another, and
- wherein the ICG circuits supply the respective partial scan chains with the circuit clock signals at pieces of timing which are different from one another.
A method for controlling a semiconductor integrated circuit including a plurality of scan chains each of which includes a serial connection of a plurality of sequential circuits, the method comprising:
- supplying the scan chains with circuit clock signals for operating the sequential circuits at pieces of timing which are different between the scan chains;
- and
- causing the scan chains to perform shift register operations in an order where the scan chains are supplied with the circuit clock signals.
Dependencies are inferred from the claim text.