Machine learning delay estimation for emulation systems
AssigneeSynopsys, Inc.
InventorsYanhua Yi, Yu Yang, Jiajun Fan, Vinod Kumar Nakkala, Vijay Sundaresan, Jianfeng Huang
Life of this patent
Estimating the term…
Abstract
A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.
Claims20
A non-transitory computer readable medium comprising stored instructions for delay estimation, wherein the stored instructions, when executed by a processor, cause the processor to:
- receive a plurality of logic blocks of a design under test (DUT);
- identify a combinatorial path based on the DUT, the combinatorial path connecting one or more logic blocks of the plurality of logic blocks;
- generate a feature vector including values of one or more orthogonal features representing characteristics of the combinatorial path;
- apply a pre-trained machine learning delay model to the feature vector to determine a wire delay of the combinatorial path, the pre-trained machine learning delay model trained using (1) values of the one or more orthogonal features representing the characteristics of a plurality of combinatorial paths, and (2) measured wire delays of the plurality of combinatorial paths;
- generate a timing graph based on the wire delay of the combinatorial path;
- and
- provide the timing graph to a compiler to perform placement and routing of the DUT.
A method for delay estimation, the method comprising:
- receiving a plurality of logic blocks of a DUT;
- identifying a combinatorial path based on the DUT, the combinatorial path connecting one or more logic blocks of the plurality of logic blocks;
- generating a feature vector including values of one or more orthogonal features representing characteristics of the combinatorial path;
- applying a pre-trained machine learning delay model to the feature vector to determine a wire delay of the combinatorial path, the pre-trained machine learning delay model trained using (1) values of the one or more orthogonal features representing the characteristics of a plurality of combinatorial paths, and (2) measured wire delays of the plurality of combinatorial paths;
- generating, by a processor, a timing graph based on the delay of the combinatorial path;
- and
- providing the timing graph to a compiler for performance of placement and routing of the DUT.
A system for delay estimation, the system comprising:
- a memory;
- and
- a processor, operatively coupled with the memory, to:
- receive a plurality of logic blocks of a DUT;
- identify a combinatorial path based on the DUT, the combinatorial path connecting one or more logic blocks of the plurality of logic blocks;
- generate a feature vector including values of one or more orthogonal features representing characteristics of the combinatorial path;
- apply a pre-trained machine learning delay model to the feature vector to determine a wire delay of the combinatorial path, the pre-trained machine learning delay model trained using (1) values of one or more orthogonal features representing the characteristics of a plurality of combinatorial paths, and (2) measured wire delay of the plurality of combinatorial paths;
- generate a timing graph based on a delay of the combinatorial path;
- and
- provide the timing graph to a compiler to perform placement and routing of the DUT.
Dependencies are inferred from the claim text.