G01R 31/318364
As a result of hardware simulation
Official title: {as a result of hardware simulation, e.g. in an HDL environment (computer-aided simulation of circuits G06F30/3308)}
G01R31/318364 (As a result of hardware simulation) appears on 183 US grants and 153 published applications in this corpus.
Search patents in G01R- Granted patents
- 183
- Published applications
- 153
- Assignees
- 89
- Inventors
- 397
- Latest grant
- 31 Mar 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1996 | 12 | 0 |
| 1997 | 2 | 0 |
| 1998 | 2 | 0 |
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 7 | 0 |
| 2002 | 4 | 4 |
| 2003 | 7 | 8 |
| 2004 | 6 | 15 |
| 2005 | 8 | 14 |
| 2006 | 18 | 10 |
| 2007 | 10 | 10 |
| 2008 | 10 | 14 |
| 2009 | 5 | 13 |
| 2010 | 10 | 4 |
| 2011 | 11 | 7 |
| 2012 | 10 | 9 |
| 2013 | 8 | 2 |
| 2014 | 7 | 3 |
| 2015 | 2 | 4 |
| 2016 | 4 | 6 |
| 2017 | 2 | 4 |
| 2018 | 5 | 3 |
| 2019 | 8 | 4 |
| 2020 | 7 | 4 |
| 2021 | 4 | 5 |
| 2022 | 3 | 1 |
| 2023 | 5 | 3 |
| 2024 | 2 | 3 |
| 2025 | 1 | 1 |
| 2026 | 2 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Test pattern generation systems and methods31 Mar 2026US 12,591,730 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Automatic functional test pattern generation based on DUT reference model and unique scripts24 Feb 2026US 12,561,218 B2Winbond Electronics Corp.
- Co-debug of processing conditions of logic devices23 Sep 2025US 12,422,476 B2International Business Machines Corporation
- Test pattern generation systems and methods16 Jul 2024US 12,039,247 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Reduced signaling interface method and apparatus9 Jan 2024US 11,867,756 B2Texas Instruments Incorporated
- Power-hardware-in-the-loop simulation system and method and non-transitory computer readable medium5 Mar 2026US 2026/0063713 A1National Taiwan University of Science and Technology
- Test pattern generating method and device1 Jan 2026US 2026/0002991 A1Samsung Electronics Co., Ltd.
- Co-debug of processing conditions of logic devices14 Aug 2025US 2025/0258221 A1International Business Machines Corporation
- Test pattern generation systems and methods10 Oct 2024US 2024/0338510 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Electronic device and method of testing electronic device27 Jun 2024US 2024/0210471 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information324US 5,801,958 ALSI Logic Corporation · 1998
- Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation252US 5,544,067 ALSI Logic Corporation · 1996
- Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information226US 5,555,201 ALSI Logic Corporation · 1996
- System and method for creating and validating structural description of electronic system219US 5,623,418 ALSI Logic Corporation · 1997
- Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models183US 5,933,356 ALSI Logic Corporation · 1999