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US 11,867,756 B2Granted
Reduced signaling interface method and apparatus
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
Claims20
An integrated circuit comprising:
- a functional circuit;
- an addressable test access port selection circuit having an address register configurable to store an address signal to enable test access;
- a first input/output terminal configurable as an input or an output and coupled to the addressable test access port selection circuit, wherein the first input/output terminal is configurable to input the address signal serially;
- a trace circuit coupled to the functional circuit and configured to generate trace data;
- a second plurality of input/output terminals, wherein each terminal of the second plurality of input/output terminals is configurable as an input or an output and coupled to the trace circuit, wherein the second plurality of input/output terminals is configurable to output the trace data;
- and
- a third plurality of input/output terminals, wherein each terminal of the third plurality of input/output terminals is configurable as an input or an output and coupled to the functional circuit,
- wherein the third plurality of input/output terminals is configurable to output data from the functional circuit.
5 more elements
A device comprising:
- a functional circuit;
- an addressable test access port selection circuit including:
- an address register configurable to store an address signal to enable test access;
- and
- an instruction register configurable to store an instruction signal for test operations;
- a first input/output terminal configurable as an input or an output and coupled to the addressable test access port selection circuit, wherein the first input/output terminal is configured as an output in response to a first instruction in the instruction register and configured as an input in response to a second instruction in the instruction register;
- a trace circuit coupled to the functional circuit and configured to generate trace data;
- a second plurality of input/output terminals, wherein each terminal is configurable as an input or an output and coupled to the trace circuit, wherein the second plurality of input/output terminals is configurable to output the trace data;
- and
- a third plurality of input/output terminals, wherein each terminal is configurable as an input or an output and coupled to the functional circuit, wherein the third plurality of input/output terminals is configurable to output data from the functional circuit.
7 more elements
A device comprising:
- a functional circuit;
- an addressable test access port selection circuit including an address register configurable to store an address signal to enable test access;
- a first input/output terminal configurable as an input or an output and coupled to the addressable test access port selection circuit, wherein the first input/output terminal is configurable to input the address signal serially;
- a trace circuit coupled to the functional circuit;
- a second plurality of input/output terminals, wherein each terminal of the second plurality of input/output terminals is configurable as an input or an output and coupled to the trace circuit;
- a third plurality of input/output terminals, wherein each terminal of the third plurality of input/output terminals is configurable as an input or an output and coupled to the functional circuit;
- a fourth input/output terminal configurable to output a return clock to be used for synchronization with an external controller;
- a fifth input/output terminal configurable as an input or an output and coupled to the trace circuit;
- and
- a sixth input/output terminal configurable as an input or an output and coupled to the trace circuit.
7 more elements
Dependencies are inferred from the claim text.