Test pattern generating method and device
AssigneeSamsung Electronics Co., Ltd.
InventorsSoyeon KANG, Kwangil So
Life of this patent
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Abstract
A test pattern generating method includes obtaining design data with respect to a circuit under test (CUT); generating, based on the design data, a first test pattern for detecting a transition delay (TD) fault and a pre-detected fault list (PDFL), wherein the PDFL comprises stuck-at (SA) faults, which respectively correspond to detectable TD faults that are included in a detectable TD fault list and are detectable through a simulation; and generating a second test pattern for detecting SA faults based on the design data and the PDFL.
Claims20
A method, performed by at least one processor, of generating a test pattern, the method comprising:
- obtaining design data with respect to a circuit under test (CUT);
- generating, based on the design data, a first test pattern for detecting a transition delay (TD) fault and a pre-detected fault list (PDFL), wherein the PDFL comprises stuck-at (SA) faults, which respectively correspond to detectable TD faults that are included in a detectable TD fault list and are detectable through a simulation;
- and
- generating, based on the design data and the PDFL, a second test pattern for detecting SA faults,
- wherein the generating the second test pattern comprises:
- generating first SA fault candidates with respect to a modeled circuit of the CUT, based on the design data;
- generating second SA fault candidates, based on the PDFL and the first SA fault candidates;
- and
- generating the second test pattern based on the second SA fault candidates.
A test pattern generating device comprising at least one processor to implement:
- a transition delay (TD) automatic test pattern generator (ATPG) module configured to obtain design data with respect to a circuit under test (CUT) and generate, based on the design data, a first test pattern for detecting a TD fault and a pre-detected fault list (PDFL), wherein the PDFL comprises stuck-at (SA) faults, which respectively correspond to detectable TD faults that are included in a detectable TD fault list and are detectable through a simulation;
- and
- a SA ATPG module configured to, based on the design data and the PDFL, generate a second test pattern for detecting SA faults,
- wherein the SA ATPG module is configured to, in generating the second test pattern:
- generate first SA fault candidates with respect to a modeled circuit of the CUT, based on the design data,
- generate second SA fault candidates, based on the PDFL and the first SA fault candidates, and
- generate the second test pattern based on the second SA fault candidates.
A system for testing a circuit under test (CUT) by using a test pattern, the system comprising:
- a test pattern generating device configured to obtain design data with respect to a CUT and generate a test pattern;
- and
- a test device configured to test the CUT by using the test pattern,
- wherein the test pattern generating device comprises at least one processor to implement:
- a transition delay (TD) automatic test pattern generator (ATPG) module configured to generate, based on the design data, a first test pattern for detecting a TD fault and a pre-detected fault list (PDFL), wherein the PDFL comprises stuck-at (SA) faults, which respectively correspond to detectable TD faults that are included in a detectable TD fault list and are detectable through a simulation;
- and
- an SA ATPG module configured to generate, based on the design data and the PDFL, a second test pattern for detecting SA faults,
- the SA ATPG module is configured to, in generating the second test pattern:
- generate first SA fault candidates with respect to a modeled circuit of the CUT, based on the design data,
- generate second SA fault candidates, based on the PDFL and the first SA fault candidates, and
- generate the second test pattern based on the second SA fault candidates.
Dependencies are inferred from the claim text.