Automatic functional test pattern generation based on DUT reference model and unique scripts

A method for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that comprises electrical circuitry, at least one input port and at least one output port, the method comprising:

• storing in a memory a high-level verification language (HVL) model of the IC, comprising a model input that models the at least one DUT input port and a model output that models the at least one DUT output port, the HVL model configured to determine, based on a logic state of the model input without modeling the electrical circuitry, a logic state of the model output responsively to a logic state of the model input;
• further storing in the memory a simulation program, configured to simulate the HVL model of the DUT and to monitor input and output ports during simulation and store monitored values in an input-output ports log file;
• and
• generating an ATE testing pattern for the DUT by running the simulation program.

A computer software product for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that comprises electrical circuitry, at least one input port and at least one output port, the product comprising a tangible non-transitory computer-readable medium in which program instructions are stored, which instructions, when read by a processor, cause the processor to:

• store in a memory a high-level verification language (HVL) model of the IC, comprising a model input that models the at least one DUT input port and a model output that models the at least one DUT output port, the HVL model configured to determine, based on a logic state of the model input without modeling the electrical circuitry, a logic state of the model output responsively to a logic state of the model input;
• further store in the memory a simulation program, configured to simulate the HVL model of the DUT and to monitor input and output ports during simulation and store monitored values in an input-output ports log file;
• and
• generate an ATE testing pattern for the DUT by running the simulation program.