H10W 72/07231
Techniques
Official title: {Techniques}
H10W72/07231 (Techniques) appears on 9,724 US grants and 10,750 published applications in this corpus.
Search patents in H10W- Granted patents
- 9,724
- Published applications
- 10,750
- Assignees
- 1,481
- Inventors
- 13,162
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 9 | 0 |
| 1977 | 9 | 0 |
| 1978 | 6 | 0 |
| 1979 | 8 | 0 |
| 1980 | 7 | 0 |
| 1981 | 11 | 0 |
| 1982 | 3 | 0 |
| 1983 | 6 | 0 |
| 1984 | 4 | 0 |
| 1985 | 4 | 0 |
| 1986 | 4 | 0 |
| 1987 | 12 | 0 |
| 1988 | 11 | 0 |
| 1989 | 17 | 0 |
| 1990 | 21 | 0 |
| 1991 | 31 | 0 |
| 1992 | 35 | 0 |
| 1993 | 45 | 0 |
| 1994 | 65 | 0 |
| 1995 | 49 | 0 |
| 1996 | 54 | 0 |
| 1997 | 72 | 0 |
| 1998 | 111 | 0 |
| 1999 | 132 | 0 |
| 2000 | 150 | 0 |
| 2001 | 184 | 67 |
| 2002 | 157 | 207 |
| 2003 | 193 | 198 |
| 2004 | 158 | 270 |
| 2005 | 185 | 340 |
| 2006 | 219 | 347 |
| 2007 | 198 | 373 |
| 2008 | 198 | 351 |
| 2009 | 207 | 348 |
| 2010 | 288 | 310 |
| 2011 | 292 | 360 |
| 2012 | 297 | 366 |
| 2013 | 332 | 447 |
| 2014 | 388 | 473 |
| 2015 | 439 | 601 |
| 2016 | 514 | 534 |
| 2017 | 576 | 563 |
| 2018 | 493 | 496 |
| 2019 | 478 | 565 |
| 2020 | 531 | 667 |
| 2021 | 492 | 651 |
| 2022 | 517 | 607 |
| 2023 | 496 | 440 |
| 2024 | 444 | 506 |
| 2025 | 398 | 364 |
| 2026 | 174 | 299 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Bonding head and bonding apparatus6 Oct 2026US 12,752,380 B2Pac Tech—Packaging Technologies GmbH
- Wire bonding using in-situ plasma treatment and apparatus for effecting the same6 Oct 2026US 12,757,746 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Wiring board, semiconductor device, and method for manufacturing semiconductor device6 Oct 2026US 12,757,762 B2Kioxia Corporation
- Package structure with wettable side surface and manufacturing method thereof, and vertical package module6 Oct 2026US 12,757,784 B2Zhuhai ACCESS Semiconductor Co., Ltd.
- Multiple plated via arrays of different wire heights on a same substrate6 Oct 2026US RE51,062 E1Adeia Semiconductor Technologies LLC
- Microelectronics package with hybrid connection to a substrate to enable reuse8 Oct 2026US 2026/0314461 A1NXP B. V.
- Semiconductor package including connection bump8 Oct 2026US 2026/0314471 A1Samsung Electronics Co., Ltd.
- Semiconductor Device and Method of Forming Fan-Out Wafer Level CPO with Through Silicon Conductive Via1 Oct 2026US 2026/0299219 A1STATS ChipPAC Pte. Ltd.
- Double sided multi chip for leaded package1 Oct 2026US 2026/0305380 A1
- Package-on-package device1 Oct 2026US 2026/0305390 A1QUALCOMM Incorporated
Most cited
By later US patents
- Three dimensional structure memory1,560US 5,915,167 AElm Technology Corporation · 1999
- 3DIC stacking device and method of manufacture962US 9,443,783 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices775US 7,157,787 B2Intel Corporation · 2007
- Semiconductor chip assemblies with fan-in leads734US 5,148,265 AIST Associates, Inc. · 1992
- Semiconductor chip assemblies having interposer and flexible lead719US 5,148,266 AIST Associates, Inc. · 1992