H10W 20/43
Layouts of interconnections
H10W20/43 (Layouts of interconnections) appears on 8,089 US grants and 9,011 published applications in this corpus.
Search patents in H10W- Granted patents
- 8,089
- Published applications
- 9,011
- Assignees
- 846
- Inventors
- 10,886
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 3 | 0 |
| 1977 | 2 | 0 |
| 1978 | 2 | 0 |
| 1979 | 1 | 0 |
| 1980 | 2 | 0 |
| 1981 | 6 | 0 |
| 1982 | 3 | 0 |
| 1983 | 3 | 0 |
| 1984 | 4 | 0 |
| 1985 | 4 | 0 |
| 1986 | 7 | 0 |
| 1987 | 14 | 0 |
| 1988 | 18 | 0 |
| 1989 | 21 | 0 |
| 1990 | 25 | 0 |
| 1991 | 20 | 0 |
| 1992 | 26 | 0 |
| 1993 | 19 | 0 |
| 1994 | 21 | 0 |
| 1995 | 23 | 0 |
| 1996 | 23 | 0 |
| 1997 | 33 | 0 |
| 1998 | 31 | 0 |
| 1999 | 39 | 0 |
| 2000 | 21 | 0 |
| 2001 | 42 | 19 |
| 2002 | 50 | 61 |
| 2003 | 55 | 50 |
| 2004 | 62 | 70 |
| 2005 | 47 | 55 |
| 2006 | 52 | 56 |
| 2007 | 32 | 56 |
| 2008 | 37 | 57 |
| 2009 | 33 | 67 |
| 2010 | 52 | 73 |
| 2011 | 70 | 98 |
| 2012 | 73 | 139 |
| 2013 | 120 | 162 |
| 2014 | 197 | 346 |
| 2015 | 360 | 596 |
| 2016 | 658 | 743 |
| 2017 | 883 | 947 |
| 2018 | 819 | 669 |
| 2019 | 727 | 732 |
| 2020 | 681 | 730 |
| 2021 | 617 | 667 |
| 2022 | 511 | 568 |
| 2023 | 471 | 521 |
| 2024 | 432 | 513 |
| 2025 | 423 | 558 |
| 2026 | 214 | 458 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Half-bridge circuit using monolithic flip-chip GAN power devices6 Oct 2026US 12,756,203 B2Navitas Semiconductor Limited
- Semiconductor die with a vertical device6 Oct 2026US 12,757,477 B2Infineon Technologies Austria AG
- Area selective deposition for zero via enclosure and extremely small metal line end space6 Oct 2026US 12,757,700 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Line extension for skip-level via landing6 Oct 2026US 12,757,709 B2International Business Machines Corporation
- Semiconductor device and electronic system including the same6 Oct 2026US 12,757,711 B2Samsung Electronics Co., Ltd.
- Metal layer layout design for circuit cells in high-density semiconductor devices8 Oct 2026US 2026/0314028 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device including cutting pattern8 Oct 2026US 2026/0314057 A1Samsung Electronics Co., Ltd.
- Layer-by-layer formation of through-substrate via8 Oct 2026US 2026/0314369 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated circuit device and method8 Oct 2026US 2026/0314376 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Manufacturing method for semiconductor device8 Oct 2026US 2026/0314379 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Method of fabricating interconnect structure for package-on-package devices1,078US 9,048,222 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Dummy structure for chip-on-wafer-on-substrate961US 9,425,126 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Semiconductor device496US 4,197,555 AFujitsu Limited · 1980
- Methods of forming wiring structures492US 9,281,277 B2Samsung Electronics Co., Ltd. · 2016
- Contact structure and memory element incorporating the same477US 6,031,287 AMicron Technology, Inc. · 2000