Dummy structure for chip-on-wafer-on-substrate

An apparatus, comprising:

• a substrate;
• a dielectric layer disposed on the substrate;
• a metal pad disposed in the dielectric layer;
• a through-silicon-via (TSV) in the substrate, wherein the TSV is located below the metal pad;
• a metal line disposed in the dielectric layer;
• a first dummy structure disposed in the dielectric layer, wherein the first dummy structure has a first width that is at least about three times greater than a second width of the metal line;
• and
• a second dummy structure disposed in the dielectric layer, wherein the second dummy structure has a third width that is at least about five times greater than the second width of the metal line.

An apparatus, comprising:

• a substrate;
• a first dielectric layer disposed over the substrate;
• a second dielectric layer disposed over the substrate;
• a plurality of through-silicon-vias (TSVs) extending through the first dielectric layer and the second dielectric layer and into the substrate;
• a plurality of metal pads disposed in the second dielectric layer, wherein each of the TSVs is located below a corresponding one of the metal pads;
• a plurality of metal lines disposed in the second dielectric layer, the metal lines having a first width;
• a plurality of first dummy structures disposed in the second dielectric layer, the first dummy structures having a second width at least three times greater than the first width of the metal lines;
• and
• a plurality of second dummy structures disposed in the second dielectric layer, the second dummy structures having a third width at least five times greater than the second width of the metal lines.