Metal layer layout design for circuit cells in high-density semiconductor devices

A method, comprising:

• forming an active region of a circuit unit cell over a substrate, the active region comprising a channel region and a source/drain region adjacent to the channel region;
• forming a gate structure comprising a gate dielectric layer over the active region and a gate electrode over the gate dielectric layer;
• forming a gate spacer extending along a sidewall of the gate structure, wherein a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the gate spacer;
• forming a source/drain feature disposed over the source/drain region of the active region;
• forming a first interlayer dielectric (ILD) layer disposed over the source/drain feature;
• forming a source/drain contact extending through the ILD layer to electrically couple to the source/drain feature, wherein an electrical conductivity of the source/drain contact is greater than an electrical conductivity of the source/drain feature;
• forming a second ILD layer over the source/drain contact;
• and
• forming a plurality of signal lines and a plurality of power lines disposed in the second ILD layer, wherein there are three adjacent power lines, referred to as first, second, and third ones of the power lines, and a number of signal lines located between the first and second ones of the power lines is less than a number of signal lines located between the second and third ones of the power lines.

A semiconductor structure, comprising:

• a transistor of a circuit unit cell comprising a gate structure interfacing at least three surfaces of a channel and an epitaxial source/drain feature interfacing a sidewall of the channel, wherein the gate structure comprises a gate dielectric layer over the channel and a gate electrode over the gate dielectric layer;
• a first dielectric layer disposed over the epitaxial source/drain feature;
• a contact feature extending through the first dielectric layer;
• a metal silicide layer between the epitaxial source/drain feature and the contact feature, wherein the contact feature is surrounded by the first dielectric layer, wherein an electrical conductivity of the metal silicide layer is between an electrical conductivity of the epitaxial source/drain feature and an electrical conductivity of the contact feature;
• and
• an interconnect structure disposed over the first dielectric layer, the interconnect structure comprising a plurality of metal power features and a plurality of metal signal features disposed in a second dielectric layer, wherein a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the second dielectric layer, and a first one and a second one of the metal signal features are positioned on opposing sides of a first one of the metal power features, and in a top view, a width of the first one of the metal signal features is different from a width of the second one of the metal signal features.