US 2026/0314376 A1Published application

Integrated circuit device and method

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsWei-Cheng KANG, Jun-YU LIN, Meng-Hung SHEN, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG

Life of this patent

Estimating the term…

Loading patent…

Abstract

An IC device includes three power rails, the second power rail aligned with a line midway between the first and third power rails, and first and second adjacent rows of cells extending between the first and third power rails. Each cell includes two active areas extending between isolation structures, first and second cells of the first row are aligned with third and fourth cells of the second row, a first active area of the first cell has a first width and a first distance from the center line, first active areas of the second and fourth cells have a second width greater than the first width and a second distance from the center line less than the first distance, and a first active area of the third cell has a third width greater than the second width and a third distance from the center line less than the second distance.

Claims20

Dependent claims

An integrated circuit (IC) device comprising:

first through third power rails extending in a first direction, wherein the second power rail is aligned with a center line midway between the first and third power rails;
and
a plurality of cells comprising first and second rows of cells adjacent to each other and extending from the first power rail to the third power rail in a second direction perpendicular to the first direction,
wherein
each cell of the plurality of cells comprises a total of two active areas extending in the first direction from a first isolation structure to a second isolation structure and having corresponding widths in the second direction,
a first active area of the two active areas of each cell is between the second active area of the two active areas and the center line,
first and second cells of the first row of cells are aligned with respective third and fourth cells of the second row of cells in the second direction,
the first active area of the first cell has a first width and a first distance from the center line,
the first active area of each of the second cell and the fourth cell has a second width greater than the first width and a second distance from the center line less than the first distance from the center line, and
the first active area of the third cell has a third width greater than the second width and a third distance from the center line less than the second distance from the center line.

7 more elements

A method of manufacturing an integrated circuit (IC) device, the method comprising:

arranging, in an IC layout diagram, a plurality of cells comprising first and second rows of cells adjacent to each other and extending in a first direction from a first power rail track extending in a second direction perpendicular to the first direction to a second power rail track extending in the second direction,
wherein
a third power rail track extends midway between the first and second power rail tracks,
each cell of the plurality of cells comprises a total of two active regions extending in the second direction from a first border to a second border and having corresponding widths in the first direction,
a first active region of the two active regions of each cell is between the second active region of the two active regions and the third power rail track,
first and second cells of the first row of cells are aligned with respective third and fourth cells of the second row of cells in the first direction,
the first active region of the first cell has a first width and a first distance from the third power rail track,
the first active region of each of the second cell and the fourth cell has a second width greater than the first width and a second distance from the third power rail track less than the first distance from the third power rail track, and
the first active region of the third cell has a third width greater than the second width and a third distance from the third power rail track less than the second distance from the third power rail track;
and
storing the IC layout diagram comprising the plurality of cells arranged relative to the first through third power rail tracks in a storage device.

8 more elements

A method of manufacturing an integrated circuit (IC) device, the method comprising:

constructing, in a semiconductor substrate, a plurality of cells comprising first and second rows of cells adjacent to each other and extending in a first direction from a first power rail track extending in a second direction perpendicular to the first direction to a second power rail track extending in the second direction,
wherein
a third power rail track extends midway between the first and second power rail tracks,
each cell of the plurality of cells comprises a total of two active areas extending in the second direction from a first isolation structure to a second isolation structure and having corresponding widths in the first direction,
a first active area of the two active areas of each cell is between the second active area of the two active areas and the third power rail track,
first and second cells of the first row of cells are aligned with respective third and fourth cells of the second row of cells in the first direction,
the first active area of the first cell has a first width and a first distance from the third power rail track,
the first active area of each of the second cell and the fourth cell has a second width greater than the first width and a second distance from the third power rail track less than the first distance from the third power rail track, and
the first active area of the third cell has a third width greater than the second width and a third distance from the third power rail track less than the second distance from the third power rail track;
and
forming first through third power rails aligned with the respective first through third power rail tracks.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/298,930Filed 13 Aug 2025
Priority: 3 Apr 2025
Published: 8 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/427
Characterised by their conductive parts: power or ground buses
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs
H10W 20/43
Characterised by their conductive parts: layouts of interconnections