Area selective deposition for zero via enclosure and extremely small metal line end space

A method of manufacturing a semiconductor device, comprising:

• forming a first conductive line having a first end over a semiconductor substrate;
• forming a second conductive line having a second end over the semiconductor substrate, wherein the first end and the second end are separated by a dielectric material;
• forming a mask pattern over the first conductive line and the second conductive line, the mask pattern to define a single opening exposing each of the first conductive line, the second conductive line and the dielectric material;
• and
• performing a first area selective deposition (ASD) of conductive material on only the exposed portions of the first and second conductive lines to form only
• a first via on the first conductive line adjacent the first end, and
• a second via on the second conductive line adjacent the second end, wherein the first ASD of the conductive material confines growth of the first via to align a first wall of the first via with a first wall of the first end, and to align a first wall of the second via with a first wall of the second end.

A method for manufacturing an integrated circuit device comprising:

• depositing a first metal pattern on a semiconductor substrate, wherein the first metal pattern comprises:
• a first conductive line extending in a first direction;
• and
• a second conductive line extending the first direction;
• depositing a first via on a first portion of the first conductive line;
• depositing a second via on a second portion of the second conductive line, wherein the first and second vias are formed simultaneously using area selective deposition into a single opening in a mask layer, and the first via is separated from the second via by a first edge-to-edge spacing;
• depositing a second metal pattern on the first via and the second via, wherein the second metal pattern comprises:
• a third conductive line contacting the first via;
• and
• a fourth conductive line contacting the second via, wherein the third conductive line is separated from the fourth conductive line by the first edge-to-edge spacing;
• and
• depositing a dielectric material between the first metal pattern and the second metal pattern after depositing the second metal pattern.