Line extension for skip-level via landing

A semiconductor structure comprising:

• a first interconnect wiring level comprising a plurality of first wiring structures, wherein at least one of the first wiring structures of the plurality of first wiring structures has a second width that is greater than a first width of each remaining first wiring structure of the plurality of first wiring structures, wherein the second width is a sum of the first width plus a width of an extension region;
• a second interconnect wiring level comprising a plurality of second wiring structures;
• a third interconnect wiring level comprising a plurality of third wiring structures, wherein the second interconnect wiring level is between the first interconnect wiring level and the third interconnect wiring level, and the plurality of first wiring structures and the plurality of third wiring structures are oriented in a same lateral direction and wherein the plurality of first wiring structures and the plurality of third wiring structures are laterally offset from each other;
• and
• a skip-level via structure contacting at least a portion of the extension region and electrically connecting the first interconnect wiring level and the third interconnect wiring level.