Semiconductor device including cutting pattern

A semiconductor device comprising:

• a substrate including a first active region and a second active region;
• first active patterns spaced apart from one another in a first direction on the first active region;
• a first device isolation layer between the first active patterns adjacent to one another;
• a first gate electrode on the first active pattern;
• and
• a first cutting pattern extending through the first gate electrode into the first device isolation layer,
• wherein the first cutting pattern includes a first portion and a second portion on the first portion,
• wherein the first portion includes a first cutting layer and a second cutting layer on the first cutting layer,
• wherein the first cutting layer and the second cutting layer have different etch selectivities with respect to at least one etch process, and
• wherein a sidewall of the first portion is spaced apart from a sidewall of the second portion in the first direction.

A semiconductor device comprising:

• a substrate including an active pattern;
• a device isolation layer defining the active pattern;
• first channel patterns spaced apart from one another in a first direction on the active pattern;
• first source/drain patterns connected to the first channel patterns;
• a cutting pattern extending vertically between the first channel patterns adjacent to one another;
• a first gate electrode connected to the first source/drain patterns;
• a gate insulating layer interposed between the first gate electrode and each of the first channel patterns;
• a gate spacer on a sidewall of the first gate electrode;
• a gate capping pattern on an upper surface of the first gate electrode;
• an interlayer insulating layer on the first source/drain pattern and the gate capping pattern;
• an active contact connected to each of the first source/drain patterns through the interlayer insulating layer;
• a gate contact connected to the gate electrode through the gate capping pattern and the interlayer insulating layer;
• and
• a first metal layer on the interlayer insulating layer, the first metal layer including a first wiring connected to the active contact and the gate contact,
• wherein the cutting pattern includes a first portion and a second portion on the first portion,
• wherein the first portion includes an upper surface exposed by the second portion, and
• wherein a level of the upper surface of the first portion is lower than a level of an upper surface of the active pattern.