H10W 80/701
Direct bonding of chips, wafers or substrates: characterised by the pads after
Official title: {characterised by the pads after the direct bonding}
H10W80/701 (Direct bonding of chips, wafers or substrates: characterised by the pads after) appears on 1,643 US grants and 2,246 published applications in this corpus.
Search patents in H10W- Granted patents
- 1,643
- Published applications
- 2,246
- Assignees
- 265
- Inventors
- 2,543
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1998 | 2 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 2 | 4 |
| 2003 | 0 | 1 |
| 2004 | 1 | 2 |
| 2005 | 2 | 6 |
| 2006 | 3 | 4 |
| 2007 | 2 | 3 |
| 2008 | 5 | 10 |
| 2009 | 2 | 4 |
| 2010 | 2 | 6 |
| 2011 | 5 | 16 |
| 2012 | 8 | 23 |
| 2013 | 12 | 35 |
| 2014 | 39 | 39 |
| 2015 | 52 | 102 |
| 2016 | 67 | 70 |
| 2017 | 70 | 83 |
| 2018 | 78 | 91 |
| 2019 | 81 | 106 |
| 2020 | 116 | 189 |
| 2021 | 154 | 281 |
| 2022 | 189 | 311 |
| 2023 | 240 | 234 |
| 2024 | 205 | 274 |
| 2025 | 194 | 209 |
| 2026 | 112 | 143 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Semiconductor package and manufacturing method thereof6 Oct 2026US 12,757,764 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Package structure with wettable side surface and manufacturing method thereof, and vertical package module6 Oct 2026US 12,757,784 B2Zhuhai ACCESS Semiconductor Co., Ltd.
- Semiconductor package and method of manufacturing the same6 Oct 2026US 12,757,790 B2Samsung Electronics Co., Ltd.
- Direct hybrid bond pad having tapered sidewall29 Sep 2026US 12,751,328 B2Adeia Semiconductor Bonding Technologies Inc.
- Semiconductor chip, semiconductor device, and semiconductor package including the same29 Sep 2026US 12,751,331 B2Samsung Electronics Co., Ltd.
- Semiconductor packages and methods for fabricating the same8 Oct 2026US 2026/0314446 A1Samsung Electronics Co., Ltd.
- Semiconductor devices having aligned front-end interface contacts and back-end interface contacts, and associated systems and methods8 Oct 2026US 2026/0314488 A1Micron Technology, Inc.
- Semiconductor package and method of manufacturing the semiconductor package1 Oct 2026US 2026/0305403 A1Samsung Electronics Co., Ltd.
- Multi-wafer bonding for nand scaling1 Oct 2026US 2026/0305424 A1SanDisk Technologies LLC
- Method of manufacturing 3dic package comprising a plurality of discrete device dies bonding to a wafer1 Oct 2026US 2026/0305486 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Method of room temperature covalent bonding315US 7,109,092 B2Ziptronix, Inc. · 2006
- Semiconductor device and associated fabrication method309US 5,753,536 AMatsushita Electric Industrial Co., Ltd. · 1998
- Methods for hybrid wafer bonding271US 8,802,538 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2014
- Independent 3D stacking269US 9,559,081 B1Apple Inc. · 2017
- Semiconductor structure and a manufacturing method thereof263US 9,859,254 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2018