Semiconductor package and method of manufacturing the same

A semiconductor package comprising:

• a first semiconductor chip comprising a first semiconductor device;
• a second semiconductor chip comprising a second semiconductor device;
• and
• a bonding structure between the first semiconductor chip and the second semiconductor chip, the bonding structure comprising:
• a first bonding insulating layer on the first semiconductor chip;
• a first bonding pad in a first pad opening portion of the first bonding insulating layer and comprising a first conductive barrier layer and a first pad metal layer;
• a second bonding insulating layer on the first semiconductor chip and in contact with the first bonding insulating layer;
• and
• a second bonding pad in a second pad opening portion of the second bonding insulating layer and comprising a second conductive barrier layer and a second pad metal layer, wherein an upper surface of the second pad metal layer is in contact with an upper surface of the first pad metal layer,
• wherein a portion of the first conductive barrier layer is in contact with the second conductive barrier layer on an outer edge of the upper surface of the first pad metal layer.

A semiconductor package comprising:

• a first semiconductor chip comprising a first semiconductor device and a plurality of through electrodes;
• a second semiconductor chip comprising a second semiconductor device;
• a bonding structure between the first semiconductor chip and the second semiconductor chip, the bonding structure comprising:
• a first bonding insulating layer on the first semiconductor chip;
• a first bonding pad in a first pad opening portion of the first bonding insulating layer and comprising a first conductive barrier layer and a first pad metal layer;
• a second bonding insulating layer on the first semiconductor chip and in contact with the first bonding insulating layer;
• and
• a second bonding pad in a second pad opening portion of the second bonding insulating layer and comprising a second conductive barrier layer and a second pad metal layer, wherein an upper surface of the second pad metal layer is in contact with an upper surface of the first pad metal layer, and a part of the first conductive barrier layer is in contact with the second conductive barrier layer on an edge of the upper surface of the first pad metal layer;
• a molding layer surrounding a side surface of the first semiconductor chip;
• and
• a connection pillar penetrating the molding layer and electrically connected to the second semiconductor chip.