Semiconductor chip, semiconductor device, and semiconductor package including the same

A semiconductor device comprising:

• a first semiconductor chip, the first semiconductor chip comprising:
• a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view;
• a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer:
• a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode;
• a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate:
• a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode,
• a second semiconductor chip mounted on the first semiconductor chip;
• and
• a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip,
• wherein the first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view,
• wherein the second semiconductor chip comprises:
• a second semiconductor substrate having a third surface and a fourth surface opposite to the third surface, and having a second active layer adjacent to the third surface, the second semiconductor substrate having a quadrangle shape from a plan view;
• a second through electrode penetrating at least a portion of the second semiconductor substrate and connected to the second active layer;
• a fourth chip connection pad on the fourth surface of the second semiconductor substrate and connected to the second through electrode;
• a second dummy pattern positioned outside the fourth chip connection pad on the fourth surface of the second semiconductor substrate from the plan view, the second dummy pattern comprising a line pattern extending horizontally along the fourth surface of the second semiconductor substrate;
• a third chip connection pad on the third surface of the second semiconductor substrate and connected to the second through electrode;
• and a first connection terminal attached to the third chip connection pad to connect the third chip connection pad to the second chip connection pad, wherein the second dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the second semiconductor substrate from the plan view, and
• wherein the first adhesive layer surrounds the second chip connection pad, the third chip connection pad, the first connection terminal, and the first dummy pattern.

A semiconductor device comprising:

• a first semiconductor chip, the first semiconductor chip comprising:
• a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view;
• a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate and connected to the first active layer;
• a plurality of second chip connection pads on the second surface of the first semiconductor substrate and respectively connected to the plurality of first through electrodes;
• a plurality of protruding line patterns positioned outside the plurality of second chip connection pads on the second surface of the first semiconductor substrate from the plan view, each line pattern of the plurality of protruding line patterns contacting and extending horizontally along the second surface of the first semiconductor substrate;
• and
• a plurality of first chip connection pads on the first surface of the first semiconductor substrate and respectively connected to the plurality of first through electrodes,
• wherein the plurality of protruding line patterns are disposed adjacent to respective sides of the quadrangle shape of the first semiconductor substrate from the plan view.