H10W 80/00
Direct bonding of chips, wafers or substrates
H10W80/00 (Direct bonding of chips, wafers or substrates) appears on 4,937 US grants and 7,755 published applications in this corpus.
Search patents in H10W- Granted patents
- 4,937
- Published applications
- 7,755
- Assignees
- 651
- Inventors
- 7,402
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 2 | 0 |
| 1990 | 2 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 2 | 0 |
| 1994 | 3 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 4 | 0 |
| 1999 | 2 | 0 |
| 2000 | 7 | 0 |
| 2001 | 2 | 3 |
| 2002 | 6 | 11 |
| 2003 | 6 | 12 |
| 2004 | 9 | 17 |
| 2005 | 11 | 23 |
| 2006 | 13 | 28 |
| 2007 | 18 | 28 |
| 2008 | 15 | 31 |
| 2009 | 18 | 30 |
| 2010 | 18 | 51 |
| 2011 | 38 | 59 |
| 2012 | 38 | 73 |
| 2013 | 66 | 100 |
| 2014 | 96 | 117 |
| 2015 | 124 | 212 |
| 2016 | 158 | 163 |
| 2017 | 191 | 196 |
| 2018 | 200 | 252 |
| 2019 | 218 | 314 |
| 2020 | 338 | 515 |
| 2021 | 423 | 727 |
| 2022 | 511 | 828 |
| 2023 | 602 | 981 |
| 2024 | 599 | 1068 |
| 2025 | 709 | 1050 |
| 2026 | 487 | 866 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- H10W 80/301Bonding techniques3,604
- H10W 80/701Direct bonding of chips, wafers or substrates: characterised by the pads after1,643
- H10W 80/011Manufacture or treatment of pads or other interconnections to be direct bonded772
- H10W 80/211Direct bonding of chips, wafers or substrates: using auxiliary members620
- H10W 80/102Controlling the environment during the bonding490
- H10W 80/161Aligning391
Recent patents
- Semiconductor package structure having a chip stack6 Oct 2026US 12,757,412 B2Changxin Memory Technologies, Inc.
- Semiconductor memory device6 Oct 2026US 12,757,413 B2Samsung Electronics Co., Ltd.
- Semiconductor device with polymer liner and method for fabricating the same6 Oct 2026US 12,757,707 B2Nanya Technology Corporation
- Barrier layers for interconnects in bonded wafers6 Oct 2026US 12,757,721 B2United Microelectronics Corp.
- Semiconductor package and manufacturing method thereof6 Oct 2026US 12,757,764 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Interconnect structure and method of forming same8 Oct 2026US 2026/0306859 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor package manufacturing methods using hybrid die bonding with spin-on siloxane materials8 Oct 2026US 2026/0308432 A1
- Semiconductor devices including global bitlines8 Oct 2026US 2026/0313881 A1Samsung Electronics Co., Ltd.
- Semiconductor device with through electrode through mold structure8 Oct 2026US 2026/0313894 A1Samsung Electronics Co., Ltd.
- Semiconductor device including ferroelectric material film and method for fabricating a semiconductor device8 Oct 2026US 2026/0313906 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- 3DIC stacking device and method of manufacture962US 9,443,783 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Methods and devices for fabricating and assembling printable semiconductor elements883US 7,622,367 B1The Board of Trustees of the University of Illinois · 2009
- Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices775US 7,157,787 B2Intel Corporation · 2007
- Stretchable semiconductor elements and stretchable electrical circuits765US 7,557,367 B2The Board of Trustees of the University of Illinois · 2009
- Process of fabricating three-dimensional semiconductor device576US 4,612,083 ANEC Corporation · 1986