US 4,612,083 AGranted

Process of fabricating three-dimensional semiconductor device

AssigneeNEC Corporation

InventorsMasaaki Yasumoto, Hiroshi Hayama, Tadayoshi Enomoto

Life of this patent

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Abstract

A process of fabricating a three-dimensional semiconductor device, comprising the steps of preparing at least two multilayer structures each including at least one semiconductor element and a conductor connected at one end to the semiconductor element and having at the other end an exposed surface, at least one of the multilayer structures further including a thermally fusible insulating adhesive layer having a surface coplanar with the exposed surface of the conductor, positioning the multilayer structures so that the exposed surfaces of the respective conductors of the multilayer structures are spaced apart from and aligned with each other, moving at least one of the multilayer structures with respect to the other until the exposed surfaces of the conductors of the multilayer structures contact each other, and heating the multilayer structures for causing the insulating adhesive layer of at least one of the multilayer structures to thermally fuse to the other multilayer structure with the semiconductor elements electrically connected together.

Claims15

Dependent claims

A process of fabricating a three-dimensional semiconductor device, comprising the steps of

(1) preparing at least two semiconductor structures each including at least one semiconductor element and a conductor electrically connected at one end to said semiconductor element and having at the other end thereof an exposed surface portion, at least one of said semiconductor structures further including a thermally fusible insulating adhesive layer having a surface substantially coplanar with said exposed surface of said conductor,
(2) positioning said semiconductor structures with respect to each other so that the exposed surface portions of the respective conductors of the semiconductor structures are spaced apart from and substantially aligned with each other,
(3) moving at least one of said semiconductor structures with respect to the other until the exposed surface portions of the respective conductors of the semiconductor structures are brought into contact with each other, and
(4) heating the semiconductor structures for causing said insulating adhesive layer of at least one of said semiconductor structures to thermally fuse to the other semiconductor structure with said semiconductor elements electrically connected together.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 06/755,987Filed 17 Jul 1985
Priority: JP 59-15059820 Jul 1984
Granted: 16 Sep 1986
Term ends: Not estimatedThe source records don’t support an estimate.

Classification28 codes

H10P 10/128
Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates: by direct semiconductor to…
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 88/01
Three-dimensional [3D] integrated devices: manufacture or treatment
H10P 72/74
For supporting or gripping: using temporarily an auxiliary support