US 12,757,413 B2Granted

Semiconductor memory device

AssigneeSamsung Electronics Co., Ltd.

InventorsHyun Geun Choi, Ki Seok Lee, Keun Nam Kim, Seok Han Park, Bo Won Yoo, Jin Woo Han

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor memory device including an active pattern on a first substrate and comprising a first and second surfaces opposite to each other in a first direction, a data storage pattern between the active pattern and the first substrate and connected to a first surface of the active pattern, a bit line on the active pattern, connected to a second surface of the active pattern, and extending in a second direction, a word line on a sidewall of the active pattern, a second substrate, a peripheral gate structure on a first surface of the second substrate, a first connection wiring structure on the first surface of the second substrate and connected to the peripheral gate structure and bit line, a second connection wiring structure on a second surface of the second substrate and a through via penetrating the second substrate and connecting the first and second connection wiring structures.

Claims20

Dependent claims

A semiconductor memory device comprising:

an active pattern disposed on a first substrate and comprising a first surface and a second surface opposite to each other in a first direction, and a first sidewall and a second sidewall opposite to each other in a second direction, the second direction intersecting the first direction;
a data storage pattern disposed between the active pattern and the first substrate and connected to the first surface of the active pattern;
a bit line disposed on the active pattern, connected to the second surface of the active pattern, and extending in the second direction;
a word line disposed on the first sidewall of the active pattern and extending in a third direction, the third direction intersecting the first direction and the second direction;
a second substrate comprising a first surface and a second surface opposite to each other in the first direction, the first surface of the second substrate facing the first substrate;
a peripheral gate structure disposed on the first surface of the second substrate;
a first connection wiring structure disposed on the first surface of the second substrate and connected to the peripheral gate structure and the bit line;
a second connection wiring structure disposed on the second surface of the second substrate;
and
a through via penetrating the second substrate and connecting the first connection wiring structure and the second connection wiring structure.

7 more elements

A semiconductor memory device comprising:

a data storage pattern disposed on a first substrate;
a first active pattern and a second active pattern disposed on the data storage pattern and spaced apart from each other in a first direction;
a first word line disposed between the first active pattern and the second active pattern on the data storage pattern and extending in a second direction, the second direction intersecting the first direction;
a second word line disposed between the first active pattern and the second active pattern on the data storage pattern, extending in the second direction, and spaced apart from the first word line in the first direction;
a gate isolation pattern disposed between the first word line and the second word line and comprising a horizontal portion and a protruding portion, the protruding portion of the gate isolation pattern protruding from the horizontal portion of the gate isolation pattern toward the data storage pattern, and a width of the horizontal portion of the gate isolation pattern in the first direction being greater than a width of the protruding portion of the gate isolation pattern in the first direction;
a bit line disposed on the first active pattern and the second active pattern and extending in the first direction;
a first bonding pad disposed on the bit line and connected to the bit line;
a second substrate comprising a first surface and a second surface opposite to each other in a third direction, the first surface of the second substrate facing the first substrate, and the third direction intersecting the first direction and the second direction;
a peripheral gate structure disposed on the first surface of the second substrate;
a first connection wiring structure disposed on the first surface of the second substrate and connected to the peripheral gate structure;
a second bonding pad connected to the first connection wiring structure and in contact with the first bonding pad;
a second connection wiring structure disposed on the second surface of the second substrate;
and
a through via penetrating the second substrate and connecting the first connection wiring structure and the second connection wiring structure.

11 more elements

A semiconductor memory device comprising:

a data storage pattern disposed on a first substrate;
a first bonding insulating layer disposed between the first substrate and the data storage pattern and containing silicon carbonitride;
first active patterns and second active patterns disposed on the data storage pattern and alternately disposed along a first direction;
back gate electrodes disposed on the data storage pattern and extending in a second direction between the first active patterns and second active patterns adjacent to each other, the second direction intersecting the first direction;
first word lines disposed adjacent to the first active patterns, respectively, and extending in the second direction;
second word lines disposed adjacent to the second active patterns, respectively, and extending in the second direction;
bit lines disposed on the first active patterns and the second active patterns and extending in the first direction;
shielding conductive lines disposed on the first active patterns and the second active patterns and disposed between the bit lines adjacent in the second direction;
first bonding pads disposed on the bit lines and connected to the bit lines;
a second substrate comprising a first surface and a second surface opposite to each other in a third direction, the first surface of the second substrate facing the first substrate, and the third direction intersecting the first direction and the second direction;
a peripheral gate structure disposed on the first surface of the second substrate;
a first connection wiring structure disposed on the first surface of the second substrate and connected to the peripheral gate structure;
second bonding pads connected to the first connection wiring structure and in contact with the first bonding pads;
a second connection wiring structure disposed on the second surface of the second substrate;
and
a through via penetrating the second substrate and connecting the first connection wiring structure and the second connection wiring structure.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/495,519Filed 26 Oct 2023
Priority: KR 10-2023-00290656 Mar 2023
Published: US 2024/0306404 A112 Sep 2024
Granted: 6 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 80/00
Assemblies of multiple devices comprising at least one memory device covered by
H10B 12/33
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: the capacitor extending under the transistor
H10B 12/482
Data lines or contacts therefor: bit lines
H10B 12/485
Data lines or contacts therefor: bit line contacts