Semiconductor package structure having a chip stack

A semiconductor package structure comprising:

• a first base;
• a first semiconductor chip connected to the first base;
• a second semiconductor chip stack structure located on the first semiconductor chip, the second semiconductor chip stack structure comprising a plurality of second semiconductor chips stacked in sequence in a first direction, the second semiconductor chip stack structure being provided with a plurality of first leads on one of the second semiconductor chips located at outermost of the second semiconductor chip stack structure in the first direction, wherein the first direction is a direction parallel to a plane of the first base;
• and
• at least one second base, signal lines in the at least one second base being connected to the plurality of the first leads, the at least one second base being connected to the first base in a direction perpendicular to the plane of the first base;
• a plurality of through silicon vias, each of the plurality of the through silicon vias penetrating through the second semiconductor chips in the first direction;
• a plurality of third conductive bumps, each of the plurality of the third conductive bumps being located between two adjacent ones of the second semiconductor chips and correspondingly connected to the through silicon vias;
• and
• the second semiconductor chip stack structure is formed by hybrid bonding.