H10W 72/07351
Characterised by changes in properties of the die-attach connectors during connecting
Official title: {characterised by changes in properties of the die-attach connectors during connecting}
H10W72/07351 (Characterised by changes in properties of the die-attach connectors during connecting) appears on 4,775 US grants and 5,641 published applications in this corpus.
Search patents in H10W- Granted patents
- 4,775
- Published applications
- 5,641
- Assignees
- 953
- Inventors
- 8,558
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 2 | 0 |
| 1978 | 2 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 1 | 0 |
| 1984 | 1 | 0 |
| 1985 | 4 | 0 |
| 1986 | 2 | 0 |
| 1987 | 3 | 0 |
| 1988 | 1 | 0 |
| 1989 | 7 | 0 |
| 1990 | 5 | 0 |
| 1991 | 5 | 0 |
| 1992 | 11 | 0 |
| 1993 | 17 | 0 |
| 1994 | 19 | 0 |
| 1995 | 13 | 0 |
| 1996 | 16 | 0 |
| 1997 | 22 | 0 |
| 1998 | 38 | 0 |
| 1999 | 37 | 0 |
| 2000 | 59 | 0 |
| 2001 | 80 | 50 |
| 2002 | 76 | 110 |
| 2003 | 74 | 85 |
| 2004 | 93 | 115 |
| 2005 | 75 | 103 |
| 2006 | 86 | 113 |
| 2007 | 79 | 127 |
| 2008 | 73 | 120 |
| 2009 | 69 | 129 |
| 2010 | 112 | 114 |
| 2011 | 100 | 169 |
| 2012 | 106 | 167 |
| 2013 | 165 | 150 |
| 2014 | 172 | 194 |
| 2015 | 186 | 253 |
| 2016 | 205 | 285 |
| 2017 | 250 | 245 |
| 2018 | 224 | 279 |
| 2019 | 272 | 343 |
| 2020 | 295 | 500 |
| 2021 | 316 | 457 |
| 2022 | 354 | 403 |
| 2023 | 309 | 314 |
| 2024 | 288 | 368 |
| 2025 | 274 | 293 |
| 2026 | 174 | 155 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Wiring board, semiconductor device, and method for manufacturing semiconductor device6 Oct 2026US 12,757,762 B2Kioxia Corporation
- Patterned sheet MUF for complex packages and methods of producing6 Oct 2026US 12,757,781 B2Intel Corporation
- Package structure with protective lid6 Oct 2026US 12,757,797 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Multiple plated via arrays of different wire heights on a same substrate6 Oct 2026US RE51,062 E1Adeia Semiconductor Technologies LLC
- Anchor-containing underfill structures for a chip package and methods of forming the same29 Sep 2026US 12,751,304 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Lid Structure With Openings To Alleviate Leakage Of Thermal Interface Material Of A Chip Assembly8 Oct 2026US 2026/0314397 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Heat dissipation in semiconductor devices8 Oct 2026US 2026/0314410 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor Device and Method of Making a Semiconductor Package with Graphene for Die Attach1 Oct 2026US 2026/0305028 A1STATS ChipPAC Pte. Ltd.
- Redistribution layer metallic layout structure and method with warpage reduction1 Oct 2026US 2026/0305234 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor structure and methods of manufacturing the same1 Oct 2026US 2026/0305394 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Fabrication process of semiconductor package and semiconductor package390US 5,976,912 AHitachi Chemical Company, Ltd. · 1999
- Light emitting diodes including modifications for light extraction390US 6,791,119 B2Cree, Inc. · 2004
- Pad array semiconductor device with thermal conductor and process for making the same386US 5,285,352 AMotorola, Inc. · 1994
- Wafer level stack structure for system-in-package and method thereof377US 7,215,033 B2Samsung Electronics Co., Ltd. · 2007
- Multichip module having a stacked chip arrangement358US 5,323,060 AMicron Semiconductor, Inc. · 1994