Multichip module having a stacked chip arrangement

A multichip module comprising:

• a multichip module substrate;
• a first chip, the first chip having opposed base and bonding faces, the base face being adhered to the multichip module substrate, the first chip bonding face including a central area and a plurality of bonding pads laterally peripheral to the central area;
• a second chip, the second chip having opposed base and bonding faces, the second chip bonding face including a central area and a plurality of peripheral bonding pads;
• an adhesive layer interposed between and connecting the first chip bonding face and the second chip base face, the adhesive layer having a thickness and a lateral perimeter, the lateral perimeter being positioned entirely within the central area inside of the peripheral bonding pads;
• a plurality of first loop bonding wires bonded to and between the respective first chip bonding pads and the multichip module substrate, the respective first loop bonding wires having outwardly projecting loops of a defined loop height, the loop height being defined by the distance between the first chip bonding face and the vertexes of the outwardly projecting loops of the first loop bonding wires, the thickness of the adhesive layer being greater than the loop height to displace the second chip base face in a non-contacting relationship above and with respect to the first wires;
• and
• a plurality of second loop bonding wires bonded to and between the respective second chip bonding pads and the multichip module substrate.