H10W 70/62
Characterised by their interconnections
Official title: characterised by their interconnections
H10W70/62 (Characterised by their interconnections) appears on 30,248 US grants and 36,456 published applications in this corpus.
Search patents in H10W- Granted patents
- 30,248
- Published applications
- 36,456
- Assignees
- 2,924
- Inventors
- 33,047
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 5 | 0 |
| 1977 | 8 | 0 |
| 1978 | 14 | 0 |
| 1979 | 4 | 0 |
| 1980 | 16 | 0 |
| 1981 | 11 | 0 |
| 1982 | 16 | 0 |
| 1983 | 14 | 0 |
| 1984 | 17 | 0 |
| 1985 | 23 | 0 |
| 1986 | 25 | 0 |
| 1987 | 39 | 0 |
| 1988 | 40 | 0 |
| 1989 | 59 | 0 |
| 1990 | 72 | 0 |
| 1991 | 104 | 0 |
| 1992 | 91 | 0 |
| 1993 | 110 | 0 |
| 1994 | 137 | 0 |
| 1995 | 130 | 0 |
| 1996 | 133 | 0 |
| 1997 | 181 | 0 |
| 1998 | 230 | 0 |
| 1999 | 274 | 0 |
| 2000 | 297 | 0 |
| 2001 | 366 | 207 |
| 2002 | 433 | 513 |
| 2003 | 443 | 521 |
| 2004 | 487 | 619 |
| 2005 | 434 | 721 |
| 2006 | 482 | 705 |
| 2007 | 467 | 807 |
| 2008 | 440 | 798 |
| 2009 | 505 | 771 |
| 2010 | 663 | 836 |
| 2011 | 672 | 872 |
| 2012 | 767 | 1007 |
| 2013 | 879 | 1156 |
| 2014 | 1086 | 1467 |
| 2015 | 1308 | 1571 |
| 2016 | 1535 | 1656 |
| 2017 | 1708 | 1725 |
| 2018 | 1588 | 1732 |
| 2019 | 1737 | 2144 |
| 2020 | 1850 | 2416 |
| 2021 | 1788 | 2350 |
| 2022 | 1840 | 2427 |
| 2023 | 1893 | 2429 |
| 2024 | 1823 | 2681 |
| 2025 | 1791 | 2582 |
| 2026 | 1213 | 1743 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Method of manufacturing a redistribution layer, redistribution layer, integrated circuit and methods for electrically testing and protecting the integrated circuit6 Oct 2026US 12,753,493 B2STMicroelectronics S,r.l.
- Integrated circuit package and method of manufacturing the same6 Oct 2026US 12,754,862 B2SK hynix Inc.
- Semiconductor package structure having a chip stack6 Oct 2026US 12,757,412 B2Changxin Memory Technologies, Inc.
- Package structure and manufacturing method thereof6 Oct 2026US 12,757,706 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Package substrate with open air gap structures6 Oct 2026US 12,757,739 B2Intel Corporation
- Wiring substrate8 Oct 2026US 2026/0309912 A1Ibiden Co., Ltd.
- Stepped trace design for impedance compensation of high-speed differential pair channels8 Oct 2026US 2026/0313784 A1Advanced Micro Devices, Inc.
- Package structure and method for forming the same8 Oct 2026US 2026/0313918 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Concentric dtc bumps for high density package decap solution8 Oct 2026US 2026/0313924 A1QUALCOMM Incorporated
- Semiconductor device structure and manufacturing method thereof8 Oct 2026US 2026/0314277 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Testing of semiconductor chips with microbumps1,870US 9,372,206 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Stacked semiconductor devices and methods of forming same1,870US 9,496,189 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Method of fabricating interconnect structure for package-on-package devices1,078US 9,048,222 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Package systems having interposers1,064US 9,048,233 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Methods and apparatus of wafer level package for heterogeneous integration technology1,051US 9,111,949 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015