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US 9,111,949 B2Granted
Methods and apparatus of wafer level package for heterogeneous integration technology
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Der-Chyang Yeh
Life of this patent
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Abstract
Methods and apparatus are disclosed to form a WLP device that comprises a first chip made of a first technology, and a second chip made of a second technology different from the first technology packaged together by a molding material encapsulating the first chip and the second chip. A post passivation interconnect (PPI) line may be formed on the molding material connected to a first contact pad of the first chip by a first connection, and connected to a second contact pad of the second chip by a second connection, wherein the first connection and the second connection may be a Cu ball, a Cu via, a Cu stud, or other kinds of connections.
Claims20
A device comprising:
- a first chip made of a first technology having a first contact pad, the first chip having a first passivation layer over a top surface of the first chip and the first contact pad, the first passivation layer having a bottom surface in contact with the top surface of the first chip and the first contact pad, and having a top surface opposite the bottom surface of the first passivation layer, wherein a first opening in the first passivation layer exposes the first contact pad;
- a second chip made of a second technology different from the first technology having a second contact pad, the second chip having a second passivation layer over a top surface of the second chip and the second contact pad, the second passivation layer having a bottom surface in contact with the top surface of the second chip and the second contact pad, and having a top surface opposite the bottom surface of the passivation layer, wherein a second opening in the second passivation layer exposes the second contact pad;
- a molding material encapsulating the first chip and the second chip, the molding material extending over the top surface of the first passivation layer and over the top surface of the second passivation layer;
- a first connection mounted on, and aligned directly over, the first contact pad;
- a second connection mounted on, and aligned directly over, the second contact pad;
- an insulating layer formed over the molding material and over the first and second connections, the insulating layer having openings exposing the first and second connections;
- and
- a post passivation interconnect (PPI) line on the insulating layer connected to the first contact pad by the first connection and connected to the second contact pad by the second connection;
- wherein the first connection is of a first connection mechanism type and the second connection is of a second connection mechanism type different from the first connection mechanism type, both connection mechanism types selected from a group consisting essentially of a conductive ball, a conductive via, or a conductive stud.
6 more elements
A device comprising:
- a first chip made of a first technology having a first contact pad, with a first passivation layer above the first contact pad having an opening to expose the first contact pad;
- a second chip made of a second technology different from the first technology having a second contact pad, with a second passivation layer above the second contact pad having an opening to expose the second contact pad;
- a first connection aligned directly over and mounted on the first contact pad and a second connection aligned directly over and mounted on the second contact pad, wherein the first connection is of a first connection mechanism type and the second connection is of a second connection mechanism type different from the first connection mechanism type, both connection mechanism types selected from a group consisting essentially of a conductive ball, a conductive via, or a conductive stud;
- a molding material encapsulating the first chip and the second chip together, while exposing the first connection and the second connection;
- a polymer layer on the molding material with a first opening to expose the first connection and a second opening to expose the second connection;
- and
- a post passivation interconnect (PPI) line on the polymer layer connected to the first connection in the first opening and connected to the second connection in the second opening.
4 more elements
A device comprising:
- a first chip made of a first technology having a plurality of first contact pads, with a first passivation layer above the plurality of first contact pads having openings exposing respective ones of the plurality of first contact pads;
- a second chip made of a second technology different from the first technology having a plurality of second contact pads greater in number than the plurality of first contact pads, with a second passivation layer above the plurality of second contact pads having openings exposing respective ones of the plurality of second contact pads;
- a plurality of first connections each mounted on, and aligned directly over, respective ones of the plurality of first contact pads and a plurality of second connections each mounted on, and aligned directly over, respective ones of the plurality of second contact pads, wherein each of the plurality of first connections is of a first connection mechanism type and each of the plurality of second connections is of a second connection mechanism type, the first connection mechanism type different from the second connection mechanism type, both connection mechanism types selected from a group consisting essentially of a conductive ball, a conductive via, or a conductive stud;
- a molding material encapsulating the first chip and the second chip together, a top surface of the molding material substantially planar with and exposing top surfaces of each of the plurality of first connections and each of the plurality of the second connections;
- a first polymer layer on the molding material with first openings exposing each of the plurality of first connections and second opening exposing each of the plurality of second connections;
- and
- a plurality of post passivation interconnect (PPI) lines on the first polymer layer connected to the plurality of first connections the plurality of second connections.
4 more elements
Dependencies are inferred from the claim text.