G06F 30/39
Circuit design at the physical level
Official title: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
G06F30/39 (Circuit design at the physical level) appears on 13,900 US grants and 13,025 published applications in this corpus.
Search patents in G06F- Granted patents
- 13,900
- Published applications
- 13,025
- Assignees
- 1,698
- Inventors
- 19,383
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1983 | 2 | 0 |
| 1984 | 3 | 0 |
| 1985 | 5 | 0 |
| 1986 | 19 | 0 |
| 1987 | 10 | 0 |
| 1988 | 8 | 0 |
| 1989 | 19 | 0 |
| 1990 | 13 | 0 |
| 1991 | 16 | 0 |
| 1992 | 24 | 0 |
| 1993 | 43 | 0 |
| 1994 | 48 | 0 |
| 1995 | 62 | 0 |
| 1996 | 84 | 0 |
| 1997 | 85 | 0 |
| 1998 | 136 | 0 |
| 1999 | 116 | 0 |
| 2000 | 103 | 0 |
| 2001 | 153 | 50 |
| 2002 | 201 | 183 |
| 2003 | 281 | 269 |
| 2004 | 248 | 327 |
| 2005 | 250 | 326 |
| 2006 | 380 | 377 |
| 2007 | 307 | 344 |
| 2008 | 321 | 432 |
| 2009 | 291 | 433 |
| 2010 | 390 | 464 |
| 2011 | 440 | 377 |
| 2012 | 564 | 418 |
| 2013 | 656 | 578 |
| 2014 | 870 | 771 |
| 2015 | 717 | 780 |
| 2016 | 689 | 720 |
| 2017 | 756 | 679 |
| 2018 | 623 | 605 |
| 2019 | 888 | 584 |
| 2020 | 863 | 629 |
| 2021 | 693 | 628 |
| 2022 | 489 | 637 |
| 2023 | 644 | 779 |
| 2024 | 520 | 630 |
| 2025 | 550 | 552 |
| 2026 | 320 | 453 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Mask optimization for layer accounting for overlap with other layers6 Oct 2026US 12,754,471 B2D2S, Inc.
- Mask optimization for layer based on comparison of components in layer to components in other layers6 Oct 2026US 12,754,472 B2D2S, Inc.
- Mask optimization preferentially accounting for overlap regions6 Oct 2026US 12,754,473 B2D2S, Inc.
- Concurrent mask optimization for multiple layers6 Oct 2026US 12,754,474 B2D2S, Inc.
- Machine learning based metrology for semiconductor specimens6 Oct 2026US 12,754,484 B2Applied Materials Israel Ltd.
- Method of and device for generating layout diagram8 Oct 2026US 2026/0310062 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Kernel function generation method, optical proximity correction method using the kernel function, and mask manufacturing method including the optical proximity correction method8 Oct 2026US 2026/0310064 A1Samsung Electronics Co., Ltd.
- Mask optimization accounting for more critical and less critical overlap regions8 Oct 2026US 2026/0310067 A1D2S, Inc.
- Interactively presenting for minimum overlap shapes in an ic design8 Oct 2026US 2026/0310865 A1D2S, Inc.
- Transformer-based end-to-end hotspot detection method for integrated circuit layouts8 Oct 2026US 2026/0310872 A1Nanjing University
Most cited
By later US patents
- System and methods for converting planar design to FinFET design1,326US 8,816,444 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2014
- Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors455US 6,209,123 B1Motorola, Inc. · 2001
- Method for integrated circuit mask patterning449US 9,256,709 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Multi-chip semiconductor arrangements using flip chip dies446US 5,399,898 ALSI Logic Corporation · 1995
- Parasitic capacitance extraction for FinFETs436US 8,826,213 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2014