System and methods for converting planar design to FinFET design
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsClement Hsingjen Wann, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh, Ting-Chu Ko, Chung-Hsien Chen
Life of this patent
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Abstract
A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
Claims20
A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, said method comprising:
- receiving a planar structure layout for an IC design, the planar structure layout including a plurality of planar active areas and a plurality of planar contacts, each planar contact associated with a planar active area;
- defining, using a processor, a plurality of FinFET active areas corresponding to the planar active areas
- determining if at least one of each of the plurality of FinFET active areas is smaller than the corresponding planar active area;
- determining at least the at least one of the plurality of planar contacts does not sufficiently contact corresponding FinFET active areas;
- and
- creating a metal layer comprising metal lines to connect the at least the at least one of the plurality of planar contacts to portions of corresponding FinFET active areas.
A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, said method comprising:
- receiving a planar structure layout for an IC design, the planar structure layout including a plurality of planar dummy areas, a plurality of planar active areas and a plurality of planar contacts, each planar contact corresponding to a planar active area;
- defining, using a processor, a plurality of FinFET active areas corresponding to the planar active areas, wherein at least one of the plurality of the FinFET active areas is smaller than the corresponding planar active area and wherein at least one of the plurality of planar contacts does not sufficiently contact corresponding FinFET active areas;
- defining a plurality of FinFET dummy areas corresponding to planar dummy areas;
- creating a metal layer to connect the at least one of the plurality of planar contacts to corresponding FinFET active areas;
- and
- adding dummy metal lines in the metal layer in the FinFET dummy areas.
A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, said method comprising:
- receiving a planar structure layout for an IC design, the planar structure layout including a plurality of planar active areas and a plurality of planar contacts, each planar contact associated with a planar active area;
- defining a plurality of FinFET active areas corresponding to the planar active areas;
- and
- generating, using a processor, a plurality of mandrels for each FinFET active area of the plurality of FinFET active areas, wherein generating the plurality of mandrels comprises:
- determining whether a FinFET cell is symmetrical, the FinFET cell comprising each FinFET area of the plurality of FinFET active areas, and
- generating the plurality of mandrels based on the determination of whether the FinFET is symmetrical.
Dependencies are inferred from the claim text.