Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors
AssigneeMotorola, Inc.
InventorsRobert L. Maziasz, Mohankumar Guruswamy, Srilata Raman
Life of this patent
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Abstract
A method of automatically placing transistors of a folded transistor circuit for synthesizing rows of transistors in a semiconductor layout (172). First, an initial placement of transistors is generated (802). Next, a candidate move of transistors is selected (804). Then the change in cost of the placement resulting from applying the candidate move is evaluated (806). A decision is made to accept the candidate move based on the evaluation of its cost (808). If accepted, the move is performed (810) and the cost of the placement is updated (812). Finally, a decision to terminate the process is made (814).
Claims17
A method of placing a plurality of single transistors for synthesizing a plurality of rows of transistors, each row having a row width, in a layout of a circuit using a simulated annealing algorithm, comprising:
- A) determining an initial placement of transistors;
- B) selecting a move of transistors to modify said initial placement of transistors of the layout;
- C) evaluating said move of transistors based, at least in part on a measure of channel routing density wherein the measure of channel routing density includes determining a maximum column density of a set of columns of transistors of the layout where the set of columns includes less than all columns of the layout, and wherein the measure of channel routing density is an incremental channel routing density that is a function of the previously determined channel routing density of the layout and of the maximum column density;
- D) selectively performing the move of transistors in response to said step of evaluating;
- E) selectively adjusting a simulated temperature of a simulated model of the circuit;
- F) selectively freezing the simulated model depending on the value of said simulated temperature;
- and
- G) selecting at least one new move of transistors and repeating steps (C), (D), (E), (F) and (G) until the simulated model is frozen, wherein the at least one new move changes a row width of one of the plurality of rows of transistors.
A method of placing a plurality of single transistors for synthesizing a plurality of rows of transistors in a layout of a circuit, the method comprising the steps of:
- determining a column density count for a designated portion of the layout, the column density count containing a plurality of elements, each of the plurality of elements representing a total number of column density items for the designated portion of the layout that have a common column density value;
- determining a channel routing density for the layout based on the column density count;
- and
- determining transistor placements using a simulated annealing algorithm that uses the channel routing density as part of a layout cost function.
A method of placing a plurality of transistors for synthesizing a layout of a circuit comprising:
- providing a prior transistor placement of the layout having a plurality of rows and columns;
- determining a prior channel routing density corresponding to said prior transistor placement of the layout;
- determining a modified transistor placement of the layout;
- determining a set of column density measurements for a set of columns of the modified transistor placement of the layout where the set of columns includes less than all columns of the layout;
- evaluating the modified transistor placement in relation to the prior transistor placement based on an incremental channel routing density as a layout cost metric;
- wherein
- the incremental channel routing density is a function of the previously determined prior channel routing density of the layout and is a function of the set of column density measurements.
A method of placing a plurality of single transistors for synthesizing a layout of a circuit, the layout including an initial placement of a plurality of rows and columns of transistors, the initial placement having a first column density vector, the method comprising:
- selecting a move of transistors that modifies the initial placement;
- evaluating the selected move of transistors based on a measure of channel routing density;
- performing the selected move of the transistors, the layout having a second column density vector after the selected move is performed;
- adjusting a simulated temperature of a simulated model of the layout;
- and
- determining whether the simulated model is frozen;
- wherein the first column density vector and the second column density vector are used to determine the channel routing density.
A method of placing a plurality of transistors for synthesizing a layout of a circuit comprising:
- determining an initial transistor placement;
- defining a channel routing density value, based upon a first column density vector, as a layout cost metric;
- moving the transistors individually to modify the initial transistor placement;
- and
- determining changes between the first column density vector and a second column density vector after moving the transistors to incrementally compute a new channel routing density, the new channel routing density utilized in determining whether the move of transistors is acceptable.
A semiconductor device comprising:
- a plurality of automatically placed single transistors in a layout having a plurality of rows and columns;
- wherein the plurality of single transistors are located in the layout according to an incremental channel density metric that is a function of a set of column density measurements for a set of columns of the layout where the set of columns includes less than all columns of the layout, the set of column density measurements generated during a plurality of transistor moves during synthesis of the semiconductor device.
Dependencies are inferred from the claim text.