Concurrent mask optimization for multiple layers

A non-transitory machine-readable medium storing a program which when executed by at least one processing unit modifies a mask layout for producing masks used to manufacture an integrated circuit (IC), the mask layout comprising a plurality of mask images for a plurality of layers of the IC, the program comprising sets of instructions for:

• identifying a first set of mask images corresponding to a first layer of the design layout and a second set of mask images corresponding to a second layer of the design layout;
• formulating a problem that expresses (i) correlation between desired shapes of IC components and predicted as-manufactured shapes of the IC components that are produced through wafer simulation operations and (ii) sizes of overlaps between the predicted as-manufactured shapes of IC components of the first and second layers at locations in the design layout at which the first-layer IC components are intended to connect to the second-layer IC components, wherein the IC components comprise a plurality of components on the first layer and a plurality of vias on the second layer, each via connecting a component on the first layer to a component on another layer;
• and
• iteratively solving the problem by iteratively exploring modifications to both the first and second sets of mask images in order to identify modified first and second sets of mask images that result in predicted as-manufactured shapes for the plurality of components on the first layer and the plurality of vias on the second layer that (i) sufficiently correlate to the desired shapes of the plurality of components and plurality of vias and (ii) have sufficient overlap sizes at locations at which the vias are intended to connect to the first-layer components in the design layout.