G06F 30/392
Floor-planning or layout
Official title: Floor-planning or layout, e.g. partitioning or placement
G06F30/392 (Floor-planning or layout) appears on 5,035 US grants and 5,055 published applications in this corpus.
Search patents in G06F- Granted patents
- 5,035
- Published applications
- 5,055
- Assignees
- 772
- Inventors
- 7,890
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1985 | 2 | 0 |
| 1986 | 4 | 0 |
| 1987 | 2 | 0 |
| 1988 | 1 | 0 |
| 1989 | 5 | 0 |
| 1990 | 5 | 0 |
| 1991 | 0 | 0 |
| 1992 | 7 | 0 |
| 1993 | 17 | 0 |
| 1994 | 12 | 0 |
| 1995 | 19 | 0 |
| 1996 | 27 | 0 |
| 1997 | 22 | 0 |
| 1998 | 54 | 0 |
| 1999 | 39 | 0 |
| 2000 | 28 | 0 |
| 2001 | 33 | 6 |
| 2002 | 54 | 38 |
| 2003 | 58 | 43 |
| 2004 | 51 | 48 |
| 2005 | 37 | 48 |
| 2006 | 75 | 60 |
| 2007 | 60 | 61 |
| 2008 | 62 | 79 |
| 2009 | 48 | 79 |
| 2010 | 72 | 155 |
| 2011 | 96 | 81 |
| 2012 | 164 | 91 |
| 2013 | 163 | 158 |
| 2014 | 236 | 288 |
| 2015 | 265 | 268 |
| 2016 | 255 | 287 |
| 2017 | 329 | 284 |
| 2018 | 263 | 236 |
| 2019 | 368 | 244 |
| 2020 | 364 | 295 |
| 2021 | 344 | 341 |
| 2022 | 245 | 357 |
| 2023 | 367 | 448 |
| 2024 | 289 | 398 |
| 2025 | 321 | 358 |
| 2026 | 172 | 304 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Protection of a circuit design within a design container6 Oct 2026US 12,755,059 B2Xilinx, Inc.
- Semiconductor device layout6 Oct 2026US 12,755,079 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Methods and apparatus to automate a design including routing between dice6 Oct 2026US 12,755,080 B2Intel Corporation
- Configuration of patterning process6 Oct 2026US 12,755,081 B2ASML Netherlands B. V.
- Method and system for automatically checking circuit layout of printed circuit board6 Oct 2026US 12,755,082 B2Usi Electronics (Shenzhen) Co., Ltd.
- Interactively presenting for minimum overlap shapes in an ic design8 Oct 2026US 2026/0310865 A1D2S, Inc.
- Transformer-based end-to-end hotspot detection method for integrated circuit layouts8 Oct 2026US 2026/0310872 A1Nanjing University
- Dummy fill layout optimization method and system8 Oct 2026US 2026/0310873 A1Samsung Electronics Co., Ltd.
- Methods, controllers, and machine-readable storage media for automated commissioning of equipment8 Oct 2026US 2026/0313820 A1PassiveLogic, Inc.
- Integrated circuit with back-side metal line8 Oct 2026US 2026/0313886 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Multi-chip semiconductor arrangements using flip chip dies446US 5,399,898 ALSI Logic Corporation · 1995
- Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process418US 8,887,106 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2014
- Design hierarchy-based placement383US 6,249,902 B1Silicon Perspective Corporation · 2001
- Arrangement method for logic cells in semiconductor IC device278US 5,224,057 AKabushiki Kaisha Toshiba · 1993
- Automatic communication of damage and health in detected vehicle incidents270US 9,317,983 B2AutoConnect Holdings LLC · 2016