Protection of a circuit design within a design container
AssigneeXilinx, Inc.
InventorsBin Dai Ochotta, Sudheendra Kusume, Alec J. Wong, Pradip K. Jha
Life of this patent
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Abstract
A key block can be generated from a session key used by a computer-based design tool for a circuit design by encrypting the session key using computer hardware. The key block can be divided, by the computer hardware, into a plurality of sub-blocks. A plurality of enhanced sub-blocks can be generated by the computer hardware by encrypting each sub-block of the plurality of sub-blocks with a different key of a plurality of keys corresponding to a plurality of Intellectual Property (IP) cores of the circuit design. The plurality of enhanced sub-blocks can be stored in a memory.
Claims20
A method, comprising:
- generating, by computer hardware, a key block by encrypting a session key used by a computer-based design tool to encrypt a circuit design;
- wherein the circuit design includes a plurality of Intellectual Property (IP) cores having a plurality of IP core keys, wherein each IP core has an IP core key of the plurality of IP core keys specific to the IP core that is an encryption key of the IP core;
- dividing, by the computer hardware, the key block into a plurality of sub-blocks, wherein each sub-block is a portion of the key block, and wherein the key block is divided into a number of the plurality of sub-blocks based on a number of the plurality of IP cores included in the circuit design;
- generating, by the computer hardware, a plurality of enhanced sub-blocks by encrypting each sub-block of the plurality of sub-blocks with a different IP core key of the plurality of IP core keys;
- and
- storing the plurality of enhanced sub-blocks in a memory.
A method, comprising:
- extracting a plurality of enhanced sub-blocks from a file including an encrypted circuit design;
- wherein the circuit design includes a plurality of Intellectual Property (IP) cores and each IP core has an IP core-specific IP core key that is an encryption key of the IP core;
- and
- wherein a number of the plurality of enhanced sub-blocks extracted corresponds to a number of the plurality of IP cores included in the circuit design;
- recovering a plurality of sub-blocks by decrypting each enhanced sub-block of the plurality of enhanced sub-blocks using a different IP core key, wherein each sub-block is a portion of a key block and the key block is a session key that is encrypted;
- forming the key block by concatenating the plurality of sub-blocks;
- recovering the session key by decrypting the key block using an asymmetric private key;
- and
- decrypting the encrypted circuit design using the session key.
A system, comprising:
- computer hardware configured to execute operations including:
- generating a key block by encrypting a session key used by a computer-based design tool to encrypt a circuit design;
- wherein the circuit design includes a plurality of Intellectual Property (IP) cores having a plurality of IP core keys, wherein each IP core has an IP core key of the plurality of IP core keys specific to the IP core that is an encryption key of the IP core;
- dividing the key block into a plurality of sub-blocks, wherein each sub-block is a portion of the key block, and wherein the key block is divided into a number of the plurality of sub-blocks based on a number of the plurality of IP cores included in the circuit design;
- generating a plurality of enhanced sub-blocks by encrypting each sub-block of the plurality of sub-blocks with a different IP core key of the plurality of IP core keys;
- and
- storing the plurality of enhanced sub-blocks in a memory.
Dependencies are inferred from the claim text.