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US 12,755,079 B2Granted
Semiconductor device layout
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng
Life of this patent
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Abstract
In some embodiments, portions of a pattern, generated in a layout process, of a layer in an integrated circuit, such as those of a layer of metallic power lines in a power grid (PG), are removed after the layout process through a computer-implemented process analogous to solving the N-coloring problem. Through this post-processing removal process, pattern portions can be removed so as reduce the coverage of the layer in the fabricated integrated circuit to a desired extent without producing certain harmful effects, such as severing a powerline.
Claims18
A method, comprising:
- (a) receiving, by an electronic design automation (EDA) system comprising an EDA tool comprising instructions stored in a storage medium in a computer, an integrated circuit layout comprising an active semiconductor layer comprising a plurality of semiconductor cells and a conductive power grid layer over the active semiconductor layer, the conductive power grid layer comprising a plurality of conductive lines for distributing power to the plurality of semiconductor cells;
- (b) identifying, by the electronic design automation (EDA) system, a plurality of portions of the conductive power grid layer as potentially removable from the conductive power grid layer, the identified portions each covering a respective region of a respective semiconductor cell, each of the potentially removable portions being positioned over a respective portion of a respective one of the plurality of semiconductor cells;
- (c) for each pair of the potentially removable portions, determining, by the electronic design automation (EDA) system, that the pair of potentially removable portions bear a spatial relationship with each other that satisfies at least one first predetermined condition;
- (d) for each one of the potentially removable portions, determining, by the electronic design automation (EDA) system, a number of other ones of the plurality of potentially removable portions with which it bears a spatial relationship that satisfies at least the first predetermined condition;
- (e) selecting, by the electronic design automation (EDA) system, a subset of the plurality of potentially removable portions as being removable from the conductive power grid layer at least in part based on the number of other ones of the plurality of potentially removable portions with which each one of the plurality of potentially removable portions bears a spatial relationship that satisfies at least the first predetermined condition;
- (f) altering, by the electronic design automation (EDA) system, the integrated circuit layout by removing at least a subset of the removable portions from the conductive power grid layer to expose the respective regions;
- and
- (g) outputting, from the electronic design automation (EDA) system, to an integrated circuit fabrication tool the altered integrated circuit layout to configure the integrated circuit fabrication tool to fabricate an integrated circuit according to the altered integrated circuit layout.
5 more elements
A system, comprising:
- a processor;
- a non-transient computer readable medium accessible by the processor, the non-transient computer readable medium storing instructions that when executed by the processor implement a method, comprising:
- receiving an integrated circuit layout indicative of an arrangement of a plurality of semiconductor cells and a conductive power grid layer comprising a plurality of conductive lines for distributing power to the plurality of semiconductor cells;
- identifying a plurality of portions of the conductive power grid layer as potentially removable from the conductive power grid layer, each of the potentially removable portions being positioned over a respective portion of a respective one of the plurality of semiconductor cells, the identified portions each covering a respective region of a respective semiconductor cell;
- for each pair of the potentially removable portions, determining whether the pair of potentially removable portions bear a spatial relationship with each other that satisfies at least one first predetermined condition;
- for each one of the potentially removable portions, determining a number of other ones of the plurality of potentially removable portions with which it bears a spatial relationship that satisfies at least the first predetermined condition;
- selecting a subset of the plurality of potentially removable portions as being removable from the conductive power grid layer as least in part based on the number of other ones of the plurality of potentially removable portions with which each one of the plurality of potentially removable portions bears a spatial relationship that satisfies at least the first predetermined condition;
- altering the integrated circuit layout by removing at least a subset of the removable portions from the conductive power grid layer to expose the respective regions;
- outputting to an integrated circuit fabrication tool an altered integrated circuit layout to configure the integrated circuit fabrication tool to fabricate an integrated circuit according to the altered integrated circuit layout;
- and
- fabricating, by the integrated circuit fabricating tool, an integrated circuit device according to the altered integrated circuit layout.
8 more elements
Dependencies are inferred from the claim text.