G06F 30/30
Circuit design
G06F30/30 (Circuit design) appears on 27,270 US grants and 24,262 published applications in this corpus.
Search patents in G06F- Granted patents
- 27,270
- Published applications
- 24,262
- Assignees
- 3,335
- Inventors
- 36,823
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 2 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 3 | 0 |
| 1982 | 1 | 0 |
| 1983 | 4 | 0 |
| 1984 | 4 | 0 |
| 1985 | 9 | 0 |
| 1986 | 25 | 0 |
| 1987 | 22 | 0 |
| 1988 | 26 | 0 |
| 1989 | 43 | 0 |
| 1990 | 43 | 0 |
| 1991 | 43 | 0 |
| 1992 | 60 | 0 |
| 1993 | 88 | 0 |
| 1994 | 107 | 0 |
| 1995 | 153 | 0 |
| 1996 | 228 | 0 |
| 1997 | 255 | 0 |
| 1998 | 366 | 0 |
| 1999 | 340 | 0 |
| 2000 | 334 | 0 |
| 2001 | 466 | 125 |
| 2002 | 553 | 540 |
| 2003 | 750 | 852 |
| 2004 | 640 | 907 |
| 2005 | 659 | 914 |
| 2006 | 1025 | 969 |
| 2007 | 852 | 914 |
| 2008 | 921 | 1135 |
| 2009 | 827 | 1073 |
| 2010 | 986 | 925 |
| 2011 | 1115 | 776 |
| 2012 | 1266 | 870 |
| 2013 | 1381 | 1027 |
| 2014 | 1504 | 1183 |
| 2015 | 1127 | 1126 |
| 2016 | 1040 | 1040 |
| 2017 | 1116 | 1018 |
| 2018 | 926 | 996 |
| 2019 | 1403 | 1029 |
| 2020 | 1414 | 1047 |
| 2021 | 1134 | 978 |
| 2022 | 867 | 1079 |
| 2023 | 1014 | 1129 |
| 2024 | 802 | 1002 |
| 2025 | 794 | 869 |
| 2026 | 531 | 739 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- G06F 30/39Circuit design at the physical level13,900
- G06F 30/32Circuit design at the digital level10,610
- G06F 30/36Circuit design at the analogue level4,556
- G06F 30/34For reconfigurable circuits2,577
- G06F 30/31Design entry466
- G06F 30/35Delay-insensitive circuit design161
- G06F 30/38Circuit design at the mixed level of analogue and digital signals106
Recent patents
- Mask optimization for layer accounting for overlap with other layers6 Oct 2026US 12,754,471 B2D2S, Inc.
- Mask optimization for layer based on comparison of components in layer to components in other layers6 Oct 2026US 12,754,472 B2D2S, Inc.
- Mask optimization preferentially accounting for overlap regions6 Oct 2026US 12,754,473 B2D2S, Inc.
- Concurrent mask optimization for multiple layers6 Oct 2026US 12,754,474 B2D2S, Inc.
- Machine learning based metrology for semiconductor specimens6 Oct 2026US 12,754,484 B2Applied Materials Israel Ltd.
- Method of and device for generating layout diagram8 Oct 2026US 2026/0310062 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Kernel function generation method, optical proximity correction method using the kernel function, and mask manufacturing method including the optical proximity correction method8 Oct 2026US 2026/0310064 A1Samsung Electronics Co., Ltd.
- Mask optimization accounting for more critical and less critical overlap regions8 Oct 2026US 2026/0310067 A1D2S, Inc.
- Efficiency-Aware Performance Bounds in SoC Design8 Oct 2026US 2026/0310855 A1Google Inc.
- Interactively presenting for minimum overlap shapes in an ic design8 Oct 2026US 2026/0310865 A1D2S, Inc.
Most cited
By later US patents
- System and methods for converting planar design to FinFET design1,326US 8,816,444 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2014
- Three dimensional memory in a system on a chip499US 8,042,082 B22011
- Multiprocessor for hardware emulation483US 5,551,013 AInternational Business Machines Corporation · 1996
- Customizable and programmable cell array466US 6,819,136 B2eASIC Corporation · 2004
- Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors455US 6,209,123 B1Motorola, Inc. · 2001