G06F 30/32
Circuit design at the digital level
Official title: Circuit design at the digital level (reconfigurable circuits G06F30/34)
G06F30/32 (Circuit design at the digital level) appears on 10,610 US grants and 8,986 published applications in this corpus.
Search patents in G06F- Granted patents
- 10,610
- Published applications
- 8,986
- Assignees
- 1,640
- Inventors
- 16,853
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1981 | 2 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 3 | 0 |
| 1986 | 6 | 0 |
| 1987 | 11 | 0 |
| 1988 | 15 | 0 |
| 1989 | 16 | 0 |
| 1990 | 24 | 0 |
| 1991 | 19 | 0 |
| 1992 | 23 | 0 |
| 1993 | 32 | 0 |
| 1994 | 32 | 0 |
| 1995 | 73 | 0 |
| 1996 | 87 | 0 |
| 1997 | 116 | 0 |
| 1998 | 155 | 0 |
| 1999 | 157 | 0 |
| 2000 | 142 | 0 |
| 2001 | 181 | 46 |
| 2002 | 208 | 214 |
| 2003 | 267 | 347 |
| 2004 | 228 | 316 |
| 2005 | 222 | 344 |
| 2006 | 353 | 369 |
| 2007 | 331 | 350 |
| 2008 | 361 | 436 |
| 2009 | 326 | 391 |
| 2010 | 359 | 288 |
| 2011 | 422 | 265 |
| 2012 | 453 | 374 |
| 2013 | 549 | 353 |
| 2014 | 543 | 352 |
| 2015 | 404 | 345 |
| 2016 | 401 | 352 |
| 2017 | 424 | 398 |
| 2018 | 332 | 408 |
| 2019 | 579 | 409 |
| 2020 | 634 | 395 |
| 2021 | 497 | 363 |
| 2022 | 382 | 402 |
| 2023 | 430 | 418 |
| 2024 | 295 | 364 |
| 2025 | 290 | 317 |
| 2026 | 224 | 370 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Compiling a tensor tiling specification to multi-dimensional data mover circuit configurations6 Oct 2026US 12,755,077 B2Xilinx, Inc.
- Methods and apparatus to automate a design including routing between dice6 Oct 2026US 12,755,080 B2Intel Corporation
- Method and system for automatically checking circuit layout of printed circuit board6 Oct 2026US 12,755,082 B2Usi Electronics (Shenzhen) Co., Ltd.
- Implementing functions in hardware29 Sep 2026US 12,748,698 B2Imagination Technologies Limited
- Scalable generative AI-based tool infrastructure29 Sep 2026US 12,748,791 B2Microsoft Technology Licensing, LLC
- Efficiency-Aware Performance Bounds in SoC Design8 Oct 2026US 2026/0310855 A1Google Inc.
- Method and system for exploring complex mega cells in integrated circuit8 Oct 2026US 2026/0310866 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Circuit topology synthesis using large language models and reinforcement learning8 Oct 2026US 2026/0310867 A1International Business Machines Corporation
- Collaborative debugging across firmware and hardware8 Oct 2026US 2026/0310868 A1International Business Machines Corporation
- Ai agent-based analysis of debugging reports for circuit design systems and applications8 Oct 2026US 2026/0310869 A1NVIDIA Corporation
Most cited
By later US patents
- Multiprocessor for hardware emulation483US 5,551,013 AInternational Business Machines Corporation · 1996
- Method of verifying integrated circuit operation by comparing stored data structures corresponding to integrated circuit logic cells379US 5,852,445 AFujitsu Limited · 1998
- Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information324US 5,801,958 ALSI Logic Corporation · 1998
- Method of using electronically reconfigurable logic circuits320US 5,036,473 AMentor Graphics Corporation · 1991
- Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system311US 5,452,239 AQuickturn Design Systems, Inc. · 1995