Method of verifying integrated circuit operation by comparing stored data structures corresponding to integrated circuit logic cells
AssigneeFujitsu Limited
InventorsSatoru Yoshikawa, Tetsu Tanizawa
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AssigneeFujitsu Limited
InventorsSatoru Yoshikawa, Tetsu Tanizawa
Estimating the term…
A method of verifying integrated circuit operation compares stored data structures which correspond to integrated circuit logic cells. Simulated graph data for a plurality of different types of logic cells are first determined by varying a plurality of factors including: the delay time of a logic cell after a signal is inputted until a signal is outputted, load capacity, and transient time of the inputted signal. The acquired graph data for each of the logic cells is then processed into data having a common origin at a common value and stored into a cell library. The processed graph data is then extracted as general-use graph data by comparing the acquired graph data with one another. A selector selects graph data which corresponds to an object of calculation from the library and an arithmetic logic unit calculates delay time of an actual logic cell based upon the selected graph data.
A method of generating general-use graph data for a plurality of different types of logic cells, comprising the steps of:
A method of logic calculation comprising the steps of:
A logic calculator comprising:
A method of storing graph data, obtained from a plurality of different types of logic cells into a cell library, the method comprising the steps of:
Dependencies are inferred from the claim text.