G06F 30/337
Design optimisation
G06F30/337 (Design optimisation) appears on 439 US grants and 468 published applications in this corpus.
Search patents in G06F- Granted patents
- 439
- Published applications
- 468
- Assignees
- 169
- Inventors
- 1,221
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 2 |
| 2003 | 0 | 2 |
| 2004 | 0 | 1 |
| 2005 | 2 | 4 |
| 2006 | 3 | 1 |
| 2007 | 1 | 0 |
| 2008 | 1 | 1 |
| 2009 | 0 | 1 |
| 2010 | 3 | 4 |
| 2011 | 1 | 3 |
| 2012 | 4 | 3 |
| 2013 | 9 | 10 |
| 2014 | 9 | 8 |
| 2015 | 9 | 7 |
| 2016 | 10 | 13 |
| 2017 | 11 | 13 |
| 2018 | 10 | 15 |
| 2019 | 19 | 22 |
| 2020 | 59 | 31 |
| 2021 | 50 | 55 |
| 2022 | 49 | 69 |
| 2023 | 58 | 63 |
| 2024 | 45 | 52 |
| 2025 | 51 | 52 |
| 2026 | 34 | 36 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Compiling a tensor tiling specification to multi-dimensional data mover circuit configurations6 Oct 2026US 12,755,077 B2Xilinx, Inc.
- Chip design method using secondary development capability of EDA software15 Sep 2026US 12,737,517 B2Batelab Co., Ltd.
- Incremental synthesis from RTL circuit designs in EDA15 Sep 2026US 12,737,526 B1Cadence Design Systems, Inc.
- Designing approximate adder circuits using reinforcement learning1 Sep 2026US 12,724,947 B1Auradine, Inc.
- Prediction of logic optimization algorithms using machine learning18 Aug 2026US 12,711,404 B1Xilinx, Inc.
- Efficiency-Aware Performance Bounds in SoC Design8 Oct 2026US 2026/0310855 A1Google Inc.
- Methods and apparatus for improving chip design with design technology co-optimization using artificial intelligence and machine learning8 Oct 2026US 2026/0310870 A1Samsung Electronics Co., Ltd.
- Circuit Implementation on Processing Circuitry10 Sep 2026US 2026/0268052 A1Altera Corporation
- Systems and methods for structured gate optimization in digital circuits3 Sep 2026US 2026/0260048 A1V.I.E.E. LLC
- Automatic parameter control for integrated circuit design flows13 Aug 2026US 2026/0236657 A1International Business Machines Corporation
Most cited
By later US patents
- Three-dimensional mask model for photolithography simulation85US 7,703,069 B1Brion Technologies, Inc. · 2010
- Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers52US 9,275,723 B2Zeno Semiconductor, Inc. · 2016
- Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers43US 9,865,332 B2Zeno Semiconductor, Inc. · 2018
- Predictable design of low power systems by pre-implementation estimation and optimization30US 7,725,848 B22010
- Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers29US 10,504,585 B2Zeno Semiconductor, Inc. · 2019