Circuit Implementation on Processing Circuitry
AssigneeAltera Corporation
InventorsKrishna Kumar Nagar, Nathan Krueger, Yi Peng, Anand Venkitasubramani
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Abstract
Systems or methods of the present disclosure may provide efficient circuit implementation on processing circuitry. The processing circuitry may include a processor, a programmable hardware, or both. The systems and methods may include determining and removing unused and/or redundant portions of predefined software and hardware description instructions before implementing associated circuitry. The implemented circuitry may perform various functions including parsing, pipelining, deparsing, temporary storage and combining, math operations, or a combination thereof, among other things.
Claims20
A data processing system, comprising:
- a memory storing code describing a plurality of predefined instruction set architecture (ISA) units, wherein each ISA unit comprises one or more instructions;
- and
- a first processor executing instructions to generate a design for a processor circuit of a second processor to perform specified operations by removing one or more extraneous instructions to cause the second processor based on the specified operations to use a reduced-set ISA unit rather than at least one predefined ISA unit of the plurality of predefined ISA units to perform a function by implementing the design.
A method, comprising:
- storing, by a first processor, code describing a plurality of predefined instruction set architecture (ISA) units, wherein each ISA unit comprises one or more instructions;
- determining, by the first processor, one or more predefined ISA units of the plurality of predefined ISA units to be used by a second processor in performing a first function;
- and
- generating, by the first processor, a modified ISA unit based on replacing at least one instruction of at least one predefined ISA unit of the one or more predefined ISA units with one or more alternative instructions to replace a function of the at least one instruction with a function of the one or more alternative instructions when executed on the second processor.
A non-transitory, computer-readable medium comprising computer-executable instructions that, when executed, are configured to cause a first processor to:
- store code describing a plurality of predefined instruction set architecture (ISA) units, wherein each ISA unit comprises one or more instructions;
- determining one or more predefined ISA units of the plurality of predefined ISA units to be used by a second processor in performing a first function;
- and
- generating a modified ISA unit based on replacing at least one instruction of at least one predefined ISA unit of the one or more predefined ISA units with one or more alternative instructions to replace a function of the at least one instruction with a function of the one or more alternative instructions when executed on the second processor.
Dependencies are inferred from the claim text.