Predictable design of low power systems by pre-implementation estimation and optimization

A system for designing a low power circuit that implements specified functionality, said system comprising:

• a processor system;
• and
• a storage system storing:
• an activity estimator module programmed to cause the processor system to:
• analyze code for an algorithmic description of the specified functionality to generate a design representation of the circuit at the algorithmic level;
• automatically instrument the code for the algorithmic description so as to capture data streams during execution of the algorithmic description;
• and
• execute the instrumented code to generate an activity profile for the algorithmic description, wherein said activity profile includes data traces of at least a portion of the executed algorithm;
• an architecture estimator module programmed to cause the processor system to use the design representation and a target architecture template to generate an initial hardware design that is an estimate of hardware resources necessary to implement the specified functionality, said storage system also storing power models for the hardware resources;
• and
• a power estimator module programmed to cause the processor system to compute power consumption for the initial hardware design based on the activity profile and the power models for the hardware resources.