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US 2026/0260048 A1Published application
Systems and methods for structured gate optimization in digital circuits
AssigneeV.I.E.E. LLC
InventorsSebastian T. VENTRONE, Hayden Clavie CRANFORD, JR.
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Abstract
A methodology for optimizing digital circuits by identifying recurring multi-gate logic structures within a gate-level representation, performing constraint-bounded Boolean reduction, and replacing such structures with validated structured gates. The approach enables improvements in area, performance, and power consumption while maintaining compatibility with target manufacturing technologies.
Claims18
A computer-implemented method for optimizing a digital circuit design, comprising:
- parsing a gate-level representation of the digital circuit design into a graph representation;
- identifying, within the graph representation, a plurality of candidate logic structures each comprising a recurring multi-gate subgraph;
- selecting at least one candidate logic structure of the plurality of candidate logic structures for optimization based on one or more optimization criteria;
- deriving a Boolean representation for the selected candidate logic structure;
- performing Boolean reduction on the Boolean representation to produce a reduced Boolean representation;
- generating a structured gate configured to implement the reduced Boolean representation;
- and
- replacing an instance of the selected candidate logic structure in the digital circuit design with the structured gate to produce an optimized digital circuit design.
5 more elements
A method comprising:
- selecting a subset of a logic device layout;
- generating Boolean equations from the subset of a logic device layout;
- performing a Boolean reduction on the Boolean equations to obtain a Boolean reduced function;
- generating a new logic device layout which is equivalent to the subset of the logic device layout from the Boolean reduced function.
1 more element
Dependencies are inferred from the claim text.