Back to results
US 12,737,526 B1Granted
Incremental synthesis from RTL circuit designs in EDA
AssigneeCadence Design Systems, Inc.
InventorsThaddeus Clay McCracken, Ankush Sood, Yifeng Wang
Life of this patent
Estimating the term…
Abstract
A method for incremental synthesis of a changed RTL design. A current RTL design and an implementation of a previous RTL design are processed to generate reuse information identifying one or more reusable design entities of the implementation of the previous register-transfer level design. An implementation of the current RTL design is generated by processing design entities of the current RTL design to generate synthesized logic corresponding to the design entities of the current RTL design, and combining the one or more reusable design entities with the synthesized logic based on the reuse information.
Claims20
A system comprising:
- one or more hardware processors;
- and
- a computer-readable storage medium storing instructions, which when executed by the one or more processors, cause the system to perform operations comprising:
- accessing, by the one or more hardware processors, a current register-transfer level design that comprises a plurality of design entities defined at a register-transfer level;
- accessing, by the one or more hardware processors, an implementation of a previous register-transfer level design that comprises a plurality of design entities defined at an implementation level;
- processing, by the one or more hardware processors, the current register-transfer level design and the implementation of the previous register-transfer level design to generate reuse information that identifies one or more reusable design entities, the one or more reusable design entities comprising design entities of the implementation of the previous register-transfer level design that can be reused in implementing the current register-transfer level design;
- and
- generating, by the one or more hardware processors, an implementation of the current register-transfer level design by:
- processing one or more design entities of the current register-transfer level design to generate synthesized logic corresponding to the one or more design entities of the current register-transfer level design;
- and
- combining the one or more reusable design entities with the synthesized logic based on the reuse information to generate the implementation of the current register-transfer level design.
8 more elements
A method comprising:
- accessing, by one or more hardware processors, a current register-transfer level design that comprises a plurality of design entities defined at a register-transfer level;
- accessing, by the one or more hardware processors, an implementation of a previous register-transfer level design that comprises a plurality of design entities defined at an implementation level;
- processing, by the one or more hardware processors, the current register-transfer level design and the implementation of the previous register-transfer level design to generate reuse information that identifies one or more reusable design entities, the one or more reusable design entities comprising design entities of the implementation of the previous register-transfer level design that can be reused in implementing the current register-transfer level design;
- and
- generating, by the one or more hardware processors, an implementation of the current register-transfer level design by:
- processing one or more design entities of the current register-transfer level design to generate synthesized logic corresponding to the one or more design entities of the current register-transfer level design;
- and
- combining the one or more reusable design entities with the synthesized logic based on the reuse information to generate the implementation of the current register-transfer level design.
5 more elements
A non-transitory computer-readable storage medium, the computer-readable storage medium comprising instructions that when executed by one or more hardware processors of a system, cause the system to perform operations comprising:
- accessing, by the one or more hardware processors, a current register-transfer level design that comprises a plurality of design entities defined at a register-transfer level;
- accessing, by the one or more hardware processors, an implementation of a previous register-transfer level design that comprises a plurality of design entities defined at an implementation level;
- processing, by the one or more hardware processors, the current register-transfer level design and the implementation of the previous register-transfer level design to generate reuse information that identifies one or more reusable design entities, the one or more reusable design entities comprising design entities of the implementation of the previous register-transfer level design that can be reused in implementing the current register-transfer level design;
- and
- generating, by the one or more hardware processors, an implementation of the current register-transfer level design by:
- processing one or more design entities of the current register-transfer level design to generate synthesized logic corresponding to the one or more design entities of the current register-transfer level design;
- and
- combining the one or more reusable design entities with the synthesized logic based on the reuse information to generate the implementation of the current register-transfer level design.
5 more elements
Dependencies are inferred from the claim text.