Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

A method of operating a multi-transistor, scalable SRAM cell having a single floating body transistor, said method comprising:

• providing the floating body transistor in which ground is applied to a source region of the floating body transistor and a write bit line that is separate from and independently operable of a read bit line, wherein the read bit line is connected to a read access transistor, the write bit line is connected to a write access transistor, and a read sense device is connected between the read access transistor and the floating body transistor;
• and
• applying pure logic levels on one or both of the write bit line and the read bit line;
• wherein said floating body transistor comprises
• a floating body having a first conductivity type selected from p-type and n-type conductivity types,
• said source region comprising a second conductivity type selected from said p-type and n-type conductivity types and different from said first conductivity type,
• a drain region comprising said first conductivity type, and
• a buried layer bounding said floating body comprising said second conductivity type, wherein said buried layer configured to be biased to ensure bistable operation of the floating body transistor.

A method of operating a multi-transistor, scalable SRAM cell having a single floating body transistor, said method comprising:

• providing the floating body transistor in which two [P+] contacts having a first conductivity type selected from p-type and n-type conductivity types are provided and a region having a second conductivity type selected from said p-type and n-type conductivity types and different from said first conductivity type is connected to ground;
• wherein one of two contacts having said first conductivity type is connected to a write access transistor connected to a write select line, wherein said write select line must be enabled to perform a write operation;
• and
• applying pure logic levels on at least one bit line connected to one of said write access transistor and a read access transistor in combination with operation of at least one of a write word line connected to the floating body transistor and a read word line connected to said read access transistor;
• wherein said floating body transistor comprises a floating body and a buried layer bounding said floating body, said buried layer configured to be biased to ensure bistable operation of the floating body transistor.