G06F 30/333
Design for testability [dft]
Official title: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
G06F30/333 (Design for testability [dft]) appears on 537 US grants and 524 published applications in this corpus.
Search patents in G06F- Granted patents
- 537
- Published applications
- 524
- Assignees
- 208
- Inventors
- 1,513
- Latest grant
- 18 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 1 | 0 |
| 1997 | 0 | 0 |
| 1998 | 1 | 0 |
| 1999 | 1 | 0 |
| 2000 | 1 | 0 |
| 2001 | 1 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 1 |
| 2004 | 0 | 1 |
| 2005 | 3 | 10 |
| 2006 | 7 | 4 |
| 2007 | 3 | 1 |
| 2008 | 4 | 10 |
| 2009 | 5 | 24 |
| 2010 | 7 | 9 |
| 2011 | 21 | 13 |
| 2012 | 17 | 28 |
| 2013 | 32 | 26 |
| 2014 | 46 | 22 |
| 2015 | 14 | 27 |
| 2016 | 27 | 22 |
| 2017 | 25 | 34 |
| 2018 | 25 | 36 |
| 2019 | 37 | 36 |
| 2020 | 54 | 36 |
| 2021 | 51 | 23 |
| 2022 | 41 | 39 |
| 2023 | 41 | 28 |
| 2024 | 22 | 36 |
| 2025 | 30 | 34 |
| 2026 | 19 | 24 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Systems and methods for memory randomization18 Aug 2026US 12,711,283 B1Cadence Design Systems, Inc.
- Scan chain optimization utilizing constrained single linkage clustering18 Aug 2026US 12,711,296 B2International Business Machines Corporation
- Integrated circuit chip with cores asymmetrically oriented with respect to each other21 Jul 2026US 12,688,097 B2Texas Instruments Incorporated
- Dynamic memory allocation in probing signal states21 Jul 2026US 12,688,344 B2Xilinx, Inc.
- Testability circuitry placement within an integrated circuit design30 Jun 2026US 12,670,305 B2Synopsys, Inc.
- Concurrent testing for semiconductor devices1 Oct 2026US 2026/0300593 A1Intel Corporation
- Fault diagnostics24 Sep 2026US 2026/0289059 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method for providing die-to-die testability17 Sep 2026US 2026/0278229 A1Microsoft Technology Licensing, LLC
- Accelerated circuit design test coverage closure using machine-learning based constraint randomization17 Sep 2026US 2026/0278230 A1Advanced Micro Devices, Inc.
- Compressed scan collar architecture for asynchronous finite state machines10 Sep 2026US 2026/0268055 A1STMicroelectronics International N. V.
Most cited
By later US patents
- System and method for lithography simulation212US 7,003,758 B2Brion Technologies, Inc. · 2006
- Method for manufacturing test simulation in electronic circuit design195US 5,539,652 AHewlett-Packard Company · 1996
- Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design98US 5,903,466 ASynopsys, Inc. · 1999
- Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration70US 7,302,625 B1Xilinx, Inc. · 2007
- System and method for lithography simulation62US 7,120,895 B2Brion Technologies, Inc. · 2006