Accelerated circuit design test coverage closure using machine-learning based constraint randomization

A system, comprising:

• a hardware processor;
• and
• one or more computer-readable storage mediums having program instructions stored thereon to cause the hardware processor to perform operations comprising:
• generating constraint ranges for input variables for a circuit design based on constraints for the input variables;
• generating a first value set for a verification testbench for the circuit design, wherein the first value set includes randomly generated values for the input variables constrained based on the constraint ranges;
• detecting whether the first value set is unique by comparing the first value set with training value sets of a training corpus;
• and
• in response to detecting that the first value set is unique, classifying the first value set by assigning a label selected from a plurality of labels to the first value set and adding the first value set to the training corpus.

A computer program product comprising:

• one or more computer-readable storage mediums having program instructions stored thereon, wherein the program instructions are executable by computer hardware to cause the computer hardware to initiate operations comprising:
• generating constraint ranges for input variables for a circuit design based on constraints for the input variables;
• generating a first value set for a verification testbench for the circuit design, wherein the first value set includes randomly generated values for the input variables constrained based on the constraint ranges;
• detecting whether the first value set is unique by comparing the first value set with training value sets of a training corpus;
• and
• in response to detecting that the first value set is unique, classifying the first value set by assigning a label selected from a plurality of labels to the first value set and adding the first value set to the training corpus.