US 12,688,344 B2 · Dynamic memory allocation in probing signal states

Abstract

Disclosed methods and systems include debug circuitry registering candidate sample values in a plurality of sample periods while application circuitry is active. The candidate sample values indicate states of a plurality of candidate signals of the application circuitry. Sample values of first probed signals from each sample period are written to a sample memory using a mapping based on bit-widths of the first probed signals. The sample values of the first probed signals are selected from the candidate sample values. The mapping is updated based on bit-widths of second probed signals, and sample values of the second probed signals from each sample period are written to the sample memory using the mapping. The sample values of the second probed signals are selected from the candidate sample values.

Claims20

Dependent claims

A method comprising:

registering by debug circuitry, candidate sample values in a plurality of sample periods while application circuitry is active, the candidate sample values indicating states of a plurality of candidate signals of the application circuitry;
writing sample values of first probed signals from each sample period to a sample memory using a mapping based on bit-widths of the first probed signals, wherein the sample values of the first probed signals are selected from the candidate sample values;
updating the mapping based on bit-widths of second probed signals;
and
writing sample values of the second probed signals from each sample period to the sample memory using the mapping, wherein the sample values of the second probed signals are selected from the candidate sample values.

2 more elements

A circuit arrangement, comprising:

a sample memory;
a capture circuit configured to register candidate sample values in each sample period of a plurality of sample periods while application circuitry is active, the candidate sample values indicating states of a plurality of candidate signals of the application circuitry;
and
a memory manager circuit coupled between the sample memory and the capture circuit and configured to:
write sample values of first probed signals from each sample period to the sample memory using a mapping based on bit-widths of the first probed signals, wherein the sample values of the first probed signals are selected from the candidate sample values,
update the mapping based on bit-widths of second probed signals, and
writing sample values of the second probed signals from each sample period to the sample memory using the mapping, wherein the sample values of the second probed signals are selected from the candidate sample values.

4 more elements

Dependencies are inferred from the claim text.

Dynamic memory allocation in probing signal states

Life of this patent

Dynamic memory allocation in probing signal states

Life of this patent

Abstract

Claims20