Testability circuitry placement within an integrated circuit design

A system, comprising:

• a processor;
• and
• memory storing instructions that, when executed by the processor
• cause the processor to:
• partition a portion of an integrated circuit (IC) design that comprises Design For Testability (DFT) Compressor Decompressor (CODEC) circuitry, into two or more sub-blocks based on a number of scan chains within the IC design;
• assign the scan chains to each of the two or more sub-blocks based on locations of end points within each of the scan chains;
• and
• generate a layout of the IC design by placing the two or more sub-blocks of the partitioned DFT CODEC circuitry within the IC design based on the locations of end points within the scan chains and the assigned scan chains.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• partition a portion of an integrated circuit (IC) design that comprises Design For Testability (DFT) Compressor Decompressor (CODEC) circuitry, into two or more sub-blocks based on a number of scan chains within the IC design;
• assign the scan chains to each of the two or more sub-blocks based on locations of end points within each of the scan chains;
• and
• generate a layout of the IC design by placing the two or more sub-blocks of the partitioned DFT CODEC circuitry within the IC design based on the locations of end points within the scan chains and the assigned scan chains.